The processor periodically checks the status of the IO module until it

The processor periodically checks the status of the

This preview shows page 62 - 72 out of 94 pages.

The processor periodically checks the status of the I/O module until it determines the instruction is complete With programmed I/O the performance level of the entire system is severely degraded No interrupts occur
Image of page 62
Interrupt-Driven I/O Processor issues an I/O command to a module and then goes on to do some other useful work The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor The processor executes the data transfer and then resumes its former processing More efficient than Programmed I/O but still requires active intervention of the processor to transfer data between memory and an I/O module
Image of page 63
Interrupt-Driven I/O Processor is interrupted when I/O module ready to exchange data Processor is free to do other work No needless waiting Consumes a lot of processor time because every word read or written passes through the processor
Image of page 64
Interrupt-Driven I/O Drawbacks I/O Transfer rate is limited by the speed with which the processor can test and service a device The processor is tied up in managing an I/O transfer a number of instructions must be executed for each I/O transfer
Image of page 65
Direct Memory Access (DMA) When the processor wishes to read or write data it issues a command to the DMA module containing: whether a read or write is requested the address of the I/O device involved the starting location in memory to read/write the number of words to be read/ Performed by a separate module on the system bus or incorporated into an I/O module Processor is involved only at the beginning and end of the transfer An interrupt is sent when the task is complete
Image of page 66
Direct Memory Access Structure With DMA, device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention SO I /O exchanges occur directly with memory Processor grants I/O module authority to read from or write to memory Relieves the processor responsibility for the exchange Processor is free to do other things Transfers the block of data directly to and from memory without going through the processor – Only one interrupt is generated per block , rather than the one interrupt per byte Device Controller Main Memory CPU DMA Controller Transfer
Image of page 67
Announcement Homework #1 is on the course Webpage. Due date is extended midnight Tuesday(September 19) Office Hours TTH 1-2PM
Image of page 68
69 Memory Hierarchy and Caching
Image of page 69
Memory Structure Main memory – memory that the CPU can access directly Secondary storage – extension of main memory that provides large nonvolatile memory capacity Spinning Disk Disk Controller Main Memory CPU secondary storage
Image of page 70
Trade-offs Major constrains in memory: how much? (Amount) ===> as much as possible how fast? (Speed) ===> to keep up with the CPU Memory must be able to keep up with the processor how expensive? (Expense Cost) ===> reasonable Cost of memory must be reasonable in relationship to the other components Trade-off: capacity access time cost Question?
Image of page 71
Image of page 72

You've reached the end of your free preview.

Want to read all 94 pages?

  • Fall '08
  • Staff
  • Central processing unit, Interrupt

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

Stuck? We have tutors online 24/7 who can help you get unstuck.
A+ icon
Ask Expert Tutors You can ask You can ask You can ask (will expire )
Answers in as fast as 15 minutes