detection capabilities for all patterns of errors 89 diffusing a data dependent

Detection capabilities for all patterns of errors 89

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detection capabilities for all patterns of errors [8,9] diffusing a data dependent timing using two and three dimensional asynchronous fine-grain pipelined architecture [5] We are going to build prototypes for major components of wireless high secure devices, such as cross-pipelined arrays, different kind of multipliers (including finite field multipliers), etc.
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We also plan to combine an online error detection based on robust error detecting codes [9] with an off line built-in self-testing and the data compression of test responses based on decoders for these codes. This approach will provide an additional tool for the detection of jamming attacks as well as intermittent and permanent faults [12]. References [1] E. Hess, N. Janssen, B. Meyer, and T. Schütze Information Leakage Attacks Against Smart Card Implementations of Cryptographic Algorithms and Countermeasures - A Survey. Proceedings of EUROSMART Security Conference, 2000 [2] J. Kelsey, B. Schneier, D. Wagner, and C. Hall, "Side Channel Cryptanalysis of Product Ciphers," ESORICS '98 Proceedings , 1998, pp. 97-110. [3] C. D. Walter, Montgomery’s Multiplication Technique: How to make it Smaller and Faster , Proc. Workshop on Cryptographic Hardware and Embedded Systems, (CHES 99), 1999, Lecture Notes in Computer Science, vol. 1717, pp 80-93. [4] R. Anderson Protecting Embedded Systems -The Next Ten Years. Proc. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001), LNCS 2162, 2001. [5] A.Taubin, K. Fant and J. McCardle Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing, Proceedings, 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD’2002, p.p.104-111. [6] S.-M.Yen, M.Joye Checking Before Output May Not Be Enough Against Fault- Based Cryptanalysis., IEEE Transaction on Computer, V49, No 9, 2000, pp. 967-970 [7] P. C. Kocher: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. CRYPTO '96, 16th Annual International Cryptology Conference, Proceedings. LNCS, Vol. 1109, Springer, 1996, pp. 104-113 [8] M. G. Karpovsky, P. Nagvajara, "Optimal Robust Compression of Test Responses," IEEE Trans. on Computers , Vol. 39, No. 1, pp. 138-141, January 1990. [9] M. G. Karpovsky, P. Nagvajara, "Optimal Codes for the Minimax Criterion on Error Detection," IEEE Trans. on Information Theory , November 1989. [10] M.L. Bushnell, V.D. Agrawal Essential of Electronic Testing for Digital, Memory and Mixed-signal VLSI Circuits, Kluwer, 2000. [11] S. Moore, R. Anderson, P. Cunningham, R. Mullins and G. Taylor “Improving Smart Card Security using Self-timed Circuits” Proc. of The Eighth IEEE International Symposium on Asynchronous Circuits and Systems, 2002 [12] M. G. Karpovsky, "Integrated On-Line and Off-Line Error Detection Mechanism in the Coding Theory Framework," VLSI Design , Vol. 5, No. 4, 1998, pp. 313-331.
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  • Spring '16
  • Cryptography, Side channel attack, Asynchronous circuit

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