same source as the device in its normal operating mode without additional skews

Same source as the device in its normal operating

This preview shows page 159 - 161 out of 683 pages.

same source as the device in its normal operating mode without additional skews from the test equipment or test fixtures. To use this approach, additional on-chip controller circuitry is included to control the on-chip clocks in test mode. The on-chip clock control is then verified, and at-speed test patterns are generated which apply clocks through proper control sequences to the on-chip clock circuitry and test mode controls. DFT Compiler and TetraMAX ATPG support a comprehensive set of features to ensure that: l The test mode control logic for the OCC operates correctly and has been connected properly. l Test mode clocks from the OCC circuitry can be efficiently used by TetraMAX ATPG for at- speed test generation. l OCC circuitry can operate asynchronously to shift and other clocks from the tester. OCC Definitions, Supported Flows, Supported Patterns Note the following definitions as they apply to OCC: l Reference Clocks — The frequency reference to the PLL. It must be maintained as a constantly pulsing and free-running oscillator or the circuitry will lose synchronization. l PLL Clocks — The output of the PLL. A free-running source that also runs at a constant frequency which may or may not be the same as the reference clock. OCC Background 6-2
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TetraMAX ATPG User Guide H-2013.03-SP4 l ATE Clocks — Shifts the scan chain typically slower than a reference clock. You must manually add this signal (a port) when inserting the OCC. Note that the ATE clock cannot be a reference clock, and it does not capture. l Internal Clocks — The OCC is responsible for gating and selecting the PLL clocks and ATE clocks, and for creating the internal clocks, which satisfy ATPG requirements. l External Clocks — The primary inputs of a design which clock flip-flops directly through combinational logic not generated from PLLs. OCC is supported in the following flows: l DFT Compiler-to-TetraMAX flow (for details, please see Chapter 7, “Using On-Chip Clocking,” in the DFT Compiler User Guide Vol. 1: Scan ) l Non-DFT Compiler to TetraMAX Flows: l Basic Scan with On-Chip Clocking l Adaptive Scan with On-Chip Clocking Note the following pattern support available in OCC: Format Synchronous Single Pulse Synchronous Multi-Pulse Asynchronous STIL Yes Yes Yes STIL99 Yes Yes No WGL Yes Yes No Others Yes No No OCC Limitations Note the following limitations for OCC support: l You must use generic capture procedures for internal/external clocking. For more information, see “ Creating Generic Capture Procedures ." l You cannot use the OCC from DFT Compiler with the set_delay -launch_cycle last_shift command. However, you can use it with the set_delay -launch_ cycle extra_shift command if it is used in combination with pipelined scan enable.
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