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this means that each sub circuit had to be constructed individually and the outputs from one sub circuit was put as the input of the next sub circuit as needed.IMPLEMENTATION AND CIRCUIT BUILDINGIn this lab the first step was to build the counter circuit as was shown in the design section of thisreport. The counter circuit consist of a flip-flop, a divide-by-two circuit and a series of logic gates leading to the outputs Lite_1, Lite_2, Lite_3 and Emerg. Figure 11 below shows the countercircuit that was built using the software.FIGURE 11: COUNTER CIRCUIT IMPLEMENTATION
FIGURE 12: LEFT CONTROL BOX IMPLEMENTATIONThe final step was to build the right control box circuit which quite similar to the left control box. Figure 13 shows the schematic of the right control box that was built using the software.
FIGURE 13: RIGHT CONTROL BOX IMPLEMENTATION
WAVEFORM ANALYSISThe Verilog test fixture is as follows:// Verilog test fixture schematic TBirdTestFixture.v – Feb 26, 2018.timescale 1s / 1msmodule TBird_TestFixture;// Outputs from your circuitwire BULB_L1, BULB_L2, BULB_L3, BULB_R1, BULB_R2, BULB_R3; wire CLK;// Inputs to your circuitreg L, R, B, RST, fCLK; // Generate a clock, real Time;initialbegin fCLK=0; Time=0;forever #0.5 Time=Time+0.5; //Keep track of time in sec.end //$time in ModleSim gave ps? always // (0.5 sec)/4 = 0.0625 sec.begin #0.062 fCLK=~fCLK; // Correct lack of 4 digit time resolution.#0.063 fCLK=~fCLK; // by using a slightly asymmetric clock. end// Make signals in tbirdtop visable in the test fixture.wire Emerg, LITE_1, LITE_2, LITE_3;// Emerg error corrected, Tue, Jan 8,2011assign Emerg=UUT.Emerg, LITE_1=UUT.LITE_1, LITE_2=UUT.LITE_2, LITE_3=UUT.LITE_3; // TESTS START HERE// ================================================================// Set all the switches low initiallyinitial beginL=0; R=0; B=0;// Do an initial reset to make Q0 =0 at the start of the simulation.RST = 0;#0.1 RST = 1; // Set RST high after a 0.1 s delay