Consider now the behavior of drain current I D vs drain source voltage V DS The

Consider now the behavior of drain current i d vs

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Consider now the behavior of drain current I D vs drain source voltage V DS . The gate source voltage is zero therefore V GS = 0. Suppose that V DS is gradually linearly increased linearly from 0V. I D also increases. At this point further increase in V DS do not produce corresponding increase in I D . Instead, as V DS increases, both depletion regions extend further into the channel, resulting in a no more cross section, and hence a higher channel resistance. Thus even though, there is more voltage, the resistance is also greater and the current remains relatively constant. This is called pinch off or saturation region. The current in this region is maximum current that FET can produce and designated by I DSS . (Drain to source current with gate shorted). As with all pn junctions, when the reverse voltage exceeds a certain level, avalanche breakdown of pn junction occurs and I D rises very rapidly .Consider now an N-channel JFET with a reverse gate source voltage. The additional reverse bias, pinch off will occur for smaller values of | V DS |, and the maximum drain current will be smaller. Suppose that V GS = 0 and that due of V DS at a specific point along the channel is +5V with respect to ground. Therefore reverse voltage across either p-n junction is now 5V. If V GS is decreased from 0 to
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14 1V the net reverse bias near the point is 5 - (-1) = 6V. Thus for any fixed value of V DS , the channel width decreases as V GS is made more negative. Thus I D value changes correspondingly. When the gate voltage is negative enough, the depletion layers touch each other and the conducting channel pinches off (disappears). In this case the drain current is cut off. The gate voltage that produces cut off is symbolized V GS (off) . It is same as pinch off voltage. Since the gate source junction is a reverse biased silicon diode, only very small reverse current flows through it. Ideally gate current is zero. As a result, all the free electrons from the source go to the drain i.e. I D = I S . Because the gate draws almost negligible reverse current the input resistance is very high 10's or 100's of M ohm. Therefore where high input impedance is required, JFET is preferred over BJT. The disadvantage is less control over output current i.e. FET takes larger changes in input voltage to produce changes in output current. For this reason, JFET has less voltage gain than a bipolar amplifier. Drain characteristics graph Transconductance Curves: The trans conductance curve of a JFET is a graph of output current (I D ) vs input voltage (V GS ) .
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15 Transfer characteristic curve By reading the value of I D and V GS for a particular value of V DS , the trans conductance curve can be plotted. The transconductance curve is a part of parabola. It has an equation of 2 ) ( 1 Off GS GS DSS D V V I I Data sheet provides only I DSS and V GS (off) value. Using these values the transconductance curve can be plotted.
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