ticom SPRS439HJUNE 2007REVISED MARCH 201065 Emulator Connection Without Signal

Ticom sprs439hjune 2007revised march 201065 emulator

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SPRS439H–JUNE 2007–REVISED MARCH 2010 6.5 Emulator Connection Without Signal Buffering for the DSP Figure 6-3 shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP Controllers CPU and Instruction Set Reference Guide (literature number SPRU160 ). Figure 6-3. Emulator Connection Without Signal Buffering for the DSP Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 123 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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Transmission Line 4.0 pF 1.85 pF Z0 = 50 29 Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test 42 3.5 nH Device Pin (B) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6.6 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their Letters and symbols and their meanings: meanings: a access time H High c cycle time (period) L Low d delay time V Valid Unknown, changing, or don't care f fall time X level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.6.1 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.6.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
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