Transmission Line4.0 pF1.85 pFZ0 = 50 Ω(Α29Tester Pin ElectronicsData Sheet Timing Reference PointOutputUnderTest42 Ω3.5 nHDevice Pin(B)TMS320F28335, TMS320F28334, TMS320F28332TMS320F28235, TMS320F28234, TMS320F28232SPRS439H–JUNE 2007–REVISED MARCH 20106.6Timing Parameter SymbologyTiming parameter symbols used are created in accordance with JEDEC Standard 100. To shorten thesymbols, some of the pin names and other related terminology have been abbreviated as follows:Lowercase subscripts and theirLetters and symbols and theirmeanings:meanings:aaccess timeHHighccycle time (period)LLowddelay timeVValidUnknown, changing, or don't careffall timeXlevelhhold timeZHigh impedancerrise timesusetup timettransition timevvalid timewpulse duration (width)6.6.1General Notes on Timing ParametersAll output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such thatall output transitions for a given half-cycle occur with a minimum of skewing relative to each other.The signal combinations shown in the following timing diagrams may not necessarily represent actualcycles. For actual cycle examples, see the appropriate cycle description section of this document.6.6.2Test Load CircuitThis test load circuit is used to measure all switching characteristics provided in this document.A.Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at thedevice pin.B.The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and itstransmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used toproduce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary toadd or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
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Serial Peripheral Interface Bus, Texas Instruments Incorporated, TMS320F28335