linear control of the dead time from its minimum of 3% to 100% as the input voltage is varied from 0 V to 3.3 V, respectively. With full-range control, the output can be controlled from external sources without disrupting the error amplifiers. The dead-time control input is a relatively high-impedance input (I I < 10 μ A) and should be used where additional control of the output duty cycle is required. However, for proper control, the input must be terminated. An open circuit is an undefined condition. 9.3.4 Comparator The comparator is biased from the 5-V reference regulator. This provides isolation from the input supply for improved stability. The input of the comparator does not exhibit hysteresis, so protection against false triggering near the threshold must be provided. The comparator has a response time of 400 ns from either of the control- signal inputs to the output transistors, with only 100 mV of overdrive. This ensures positive control of the output within one-half cycle for operation within the recommended 300-kHz range. Copyright © 1983–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TL494
TL494 SLVS074G –JANUARY 1983–REVISED JANUARY 2015 Feature Description (continued) 9.3.5 Pulse-Width Modulation (PWM) The comparator also provides modulation control of the output pulse width. For this, the ramp voltage across timing capacitor C T is compared to the control signal present at the output of the error amplifiers. The timing capacitor input incorporates a series diode that is omitted from the control signal input. This requires the control signal (error amplifier output) to be ∼ 0.7 V greater than the voltage across C T to inhibit the output logic, and ensures maximum duty cycle operation without requiring the control voltage to sink to a true ground potential. The output pulse width varies from 97% of the period to 0 as the voltage present at the error amplifier output varies from 0.5 V to 3.5 V, respectively. 9.3.6 Error Amplifiers Both high-gain error amplifiers receive their bias from the V I supply rail. This permits a common-mode input voltage range from –0.3 V to 2 V less than V I . Both amplifiers behave characteristically of a single-ended single- supply amplifier, in that each output is active high only. This allows each amplifier to pull up independently for a decreasing output pulse-width demand. With both outputs ORed together at the inverting input node of the PWM comparator, the amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased low by a current sink to provide maximum pulse width out when both amplifiers are biased off. 9.3.7 Output-Control Input The output-control input determines whether the output transistors operate in parallel or push-pull. This input is the supply source for the pulse-steering flip-flop. The output-control input is asynchronous and has direct control over the output, independent of the oscillator or pulse-steering flip-flop. The input condition is intended to be a fixed condition that is defined by the application. For parallel operation, the output-control input must be grounded. This disables the pulse-steering flip-flop and inhibits its outputs. In this mode, the pulses seen at the
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- Winter '19
- Pedro Mora
- Operational Amplifier, Trigraph, power supply, Switched-mode power supply, Texas Instruments Incorporated