7: Power56Leakage Control•Leakage and delay trade off–Aim for low leakage in sleep and low delay in active mode•To reduce leakage:–Increase Vt: multiple Vt•Use low Vtonly in critical circuits–Increase Vs: stack effect•Input vector controlin sleep–Decrease Vb•Reverse body biasin sleep•Or forward body bias in active mode
Capacitance Model for CMOS
Estimation of Interconnect Parasitics
•The transmission-line effects have not been a serious concern in CMOS VLSI chips until recently, since the gate delays due to capacitive load components dominated the line delay in most cases. •But as the fabrication technologies move to finer submicron design rules, the intrinsic gate delays tend to decrease significantly. •Worst-case line length on a chip increases mainly due to increasing chip complexity, thus, the importance of interconnect delay increases in submicron technologies.•In addition, as the widths of metal lines shrink, the transmission line effects and signal coupling between neighbouring lines become even more pronounced.
Which interconnections in a chip may cause serious problems in terms of delay?•Each module contains a relatively large number of local connections between itsfunctional blocks, logic gates, and transistors. So we have short distance intra-module connections.•Fair amount of longer connections between the modules on a chip, the so-called inter-module connections ( MORE PROBLEMATIC)
Ex: Six interconnect lines running on 3 different levels