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# A what is the size of the memory for this computer b

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a. What is the size of the memory for this computer? b. What is the size of the memory if the addressable memory word is increased to 16 bits c. By how many addresses AR and PC are incremented to point to the next instruction, if the memory word is 8 bits d. By how many addresses AR and PC are incremented to point to the next instruction, if the memory word is 16 bits e. How many opcodes can be generated by this computer? Memory size Memory size Address step Address step opcodes

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6- The contents of PC, AC and the memory are shown below: (all numbers are in hexadecimal). Memory Address (HEX) Contents (HEX) Register Name Contents (HEX) 2AC 8753 PC 2AB 753 0967 AC 8BC3 967 8CA9 - - a. Decode the instruction that will be fetched when PC is incremented by completing the following table: b. Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the values of E, I, and the sequence counter SC in binary at the end of the instruction cycle. Insert the values in the following table; PC(HEX) AR(HEX) DR(HEX) AC(HEX) IR(HEX) E I SC 7- Complete the following table (all values are in hexadecimal). RTL AC DR IR PC AR M[AR] Initial Values CD22 F0E0 1EA1 A09 BA8 0061 CD22 F0E0 1EA1 A09 061 02FA T0: AR PC CD22 F0E0 1EA1 A09 A09 9BA8 T1: IR M[AR] , PC PC+1 T2: AR IR(0-11), I IR(15), D 0 :D 7 IR(14:12) T3:D7’IT3:AR M[AR] T4: T5: 8- Derive and label the control gates for the Load and Clear inputs of the E flipflop, using instructions listed in Table 5.6 shown in the following diagram; a- Complete Boolean expression for Load(E) b- Complete Boolean expression for Clear(E) c- Label the following diagram; Opcode(binary) I(binary) AR(HEX) RTL Load(E)= Clear(E)= Load (E) Clear(E)
9- Using Table 5.6, derive and label the control gates for the load, clear and increment inputs in PC register of the

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