Extended Instruction Pointer Contains address of next instruction to be

Extended instruction pointer contains address of next

This preview shows page 43 - 52 out of 57 pages.

Extended Instruction Pointer Contains address of next instruction to be executed EFLAGS = Extended Flags Register Contains status and control flags Each flag is a single binary bit Six 16-bit Segment Registers Support segmented memory Six segments accessible at a time Segments contain distinct contents Code Data Stack
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EFLAGS Register Status Flags Status of arithmetic and logical operations Control and System flags Control the CPU operation Programs can set and clear individual bits in the EFLAGS register
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Status Flags Carry Flag Set when unsigned arithmetic result is out of range Overflow Flag Set when signed arithmetic result is out of range Sign Flag Copy of sign bit , set when result is negative Zero Flag Set when result is zero Auxiliary Carry Flag Set when there is a carry from bit 3 to bit 4 Parity Flag Set when parity is even Least-significant byte in result contains even number of 1s
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Next ... Intel Microprocessors IA-32 Registers Instruction Execution Cycle IA-32 Memory Management
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Fetch-Execute Cycle Each machine language instruction is first fetched from the memory and stored in an Instruction Register ( IR ). The address of the instruction to be fetched is stored in a register called Program Counter or simply PC . In some computers this register is called the Instruction Pointer or IP . After the instruction is fetched, the PC (or IP ) is incremented to point to the address of the next instruction. The fetched instruction is decoded (to determine what needs to be done) and executed by the CPU.
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Instruction Execute Cycle Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value and status Deposit results in storage for later use Instruction Decode Instruction Fetch Operand Fetch Execute Writeback Result Infinite Cycle
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Instruction Execution Cycle – cont'd Instruction Fetch Instruction Decode Operand Fetch Execute Result Writeback I2 I3 I4 PC program I1 instruction register op1 op2 memory fetch ALU registers write d e c o d e execute read write (output) registers flags . . . I1
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Next ... Intel Microprocessors IA-32 Registers Instruction Execution Cycle IA-32 Memory Management
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Modes of Operation Real-Address mode (original mode provided by 8086) Only 1 MB of memory can be addressed, from 0 to FFFFF (hex) Programs can access any part of main memory MS-DOS runs in real-address mode Protected mode (introduced with the 80386 processor) Each program can address a maximum of 4 GB of memory The operating system assigns memory to each running program Programs are prevented from accessing each other’s memory Native mode used by Windows NT, 2000, XP, and Linux Virtual 8086 mode Processor runs in protected mode, and creates a virtual 8086 machine with 1 MB of address space for each running program
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  • X86, Intel

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