Setdrc clockconstraints command none of the

set_drc -clock_constraints command, none of the
ClockConstraints blocks is used.
Timing information is not provided, which means clocks are assumed to be in the order specified.
All clocks that pulse in the same frame are assumed to pulse simultaneously without disturbing
each other. The trailing edges of all clock pulses in the first frame are assumed to occur before
the leading edges of the clocks in the second frame. If these assumptions are violated in the
actual design, timing exceptions must be used to prevent simulation mismatches.
You can use the set_drc -num_pll_cycles command to specify the sequential depth of
the constraints. Procedures with a small number of frames are padded with clock-off values.
Procedures with a large number of frames are degenerated if all of the extra frames are at clock-
off values; otherwise, they are unusable. This enables the definition of multiple constraints of
different depth in a single Constraints block while ensuring that only the procedures of the
appropriate depth are used. The set_drc -num_pll_cycles and set_atpg -
capture commands must match, but they can differ from the PLLCycles declaration in the
ClockStructures block. The commands specify the sequential depth to be used in this
OCC Support in TetraMAX 6-15

TetraMAX ATPG User Guide H-2013.03-SP4
particular run, while the the PLLCycles declaration indicates the maximum sequential depth
supported by the clock controller.
Reporting Clocks
You can use the -constraints option of the report_clocks command to report
information on clocking procedures as they are used by ATPG. To report details for a given
procedure, use the report_clocks -constraints –procedure name command. To
report more detail for all procedures, use the report_clocks -constraints -all
command.
For example,
TEST> report_clocks –constraints -all
----------------------------------------------------------------
--------------
Clock Constraints constraints1:
Maximum sequential depth: 2
Defined Clocking Procedures: 3
Usable Clocking Procedures: 3
PLL clocks off Procedure: ClockOff
U0to1:
CLKIR=10010
dutm/ctrl1/U17/Z=P0
dutm/ctrl2/U19/Z=0P
--------------------
U1to0:
CLKIR=01010
dutm/ctrl1/U17/Z=0P
dutm/ctrl2/U19/Z=P0
--------------------
ClockOff:
CLKIR=00000
dutm/ctrl1/U17/Z=00
dutm/ctrl2/U19/Z=00
--------------------
Note: When procedures with different frame counts are reported, the shorter procedures are
shown with zeroes padded to the left so that all procedures are reported with the same depth.
This does not mean that the procedures should be written this way. ATPG is more efficient when
all procedures are written with as few frames as possible.
Performing ATPG with Internal Clocking Procedures
The internal clocking procedures feature fully supports two-clock optimized ATPG, basic scan
ATPG, and fast-sequential ATPG. Full-sequential ATPG is not supported and no patterns are
generated when internal clocking procedures are defined.