C each device connected to the bus is software

Info iconThis preview shows pages 6–14. Sign up to view the full content.

View Full Document Right Arrow Icon
c Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master- receivers. c It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. c More than one IC capable of initiating a data transfer can be connected to it. The I2C protocol specification states that the IC that initiates a data transfer on the bus is considered the Bus Master. Consequently, at that time, all the other ICs are regarded to be Bus Slaves. Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
Background image of page 6

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
I2C Bus – Features c Serial, 8-bit oriented, bidirectional data transfers can be made at Up to 100 kbit/s in the Standard-mode. Up to 400 kbit/s in the Fast-mode. Up to 1 Mbit/s in Fast-mode Plus. Up to 3.4 Mbit/s in the High-speed mode.
Background image of page 7
Protocol c Transfers are byte oriented, msb first c Start: SDA goes low while SCL is high c Master sends address of slave (7-bits) on next 7 clocks c Master sends read/write request bit 0-write to slave 1-read from slave c Slave ACKs by pulling SDA low on next clock c Data transfers now commence
Background image of page 8

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
I2C Bus – Terminology Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
Background image of page 9
I2C Bus – Signal Lines c The two signal lines SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor. c When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open- collector to perform the wired-AND function. c The levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are set as 30% and 70% of VDD; VIL is 0.3VDD and VIH is 0.7VDD.
Background image of page 10

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
I2C Bus – Data Validity c The data on the SDA line must be stable during the HIGH period of the clock. c The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. c One clock pulse is generated for each data bit transferred. Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
Background image of page 11
c All transactions begin with a START (S) and can be terminated by a STOP (P). c A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. c A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. c START and STOP conditions are always generated by the master. Reference : UM10204 - I2C Bus Specification & User Manual from NXP Semiconductors
Background image of page 12

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
I2C Bus – Byte Format c Every byte put on the SDA line must be 8 bits long. c
Background image of page 13
Image of page 14
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page6 / 44

c Each device connected to the bus is software addressable...

This preview shows document pages 6 - 14. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online