SCI The serial communications interface is a two wire asynchronous serial port

Sci the serial communications interface is a two wire

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SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between a DSC and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSC through the I2C module. On the 2833x/2823x, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead. 48 Functional Overview Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 3.3 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-7 . Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-8 . Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3-9 . Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible peripheral bus. See Table 3-10 . Table 3-7. Peripheral Frame 0 Registers (1) NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE (2) Device Emulation Registers 0x00 0880 – 0x00 09FF 384 EALLOW protected FLASH Registers (3) 0x00 0A80 – 0x00 0ADF 96 EALLOW protected Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 EALLOW protected ADC registers (dual-mapped) 0x00 0B00 – 0x00 0B0F 16 Not EALLOW protected 0 wait (DMA), 1 wait (CPU), read only XINTF Registers 0x00 0B20 – 0x00 0B3F 32 EALLOW protected CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 Not EALLOW protected PIE Registers 0x00 0CE0 – 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 EALLOW protected DMA Registers 0x00 1000 – 0x00 11FF 512 EALLOW protected (1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. (3) The Flash Registers are also protected by the Code Security Module (CSM). Table 3-8. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (x16) eCAN-A Registers 0x00 6000 – 0x00 61FF 512 eCAN-B Registers 0x00 6200 – 0x00 63FF 512 ePWM1 + HRPWM1 registers 0x00 6800 – 0x00 683F 64 ePWM2 + HRPWM2 registers 0x00 6840 – 0x00 687F 64 ePWM3 + HRPWM3 registers 0x00 6880 – 0x00 68BF 64 ePWM4 + HRPWM4 registers 0x00 68C0 – 0x00 68FF 64 ePWM5 + HRPWM5 registers 0x00 6900 – 0x00 693F 64 ePWM6 + HRPWM6 registers 0x00 6940 – 0x00 697F 64 eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 eCAP2 registers 0x00 6A20 – 0x00 6A3F 32 eCAP3 registers 0x00 6A40 – 0x00 6A5F 32 eCAP4 registers 0x00 6A60 – 0x00 6A7F 32 eCAP5 registers 0x00 6A80 – 0x00 6A9F 32 eCAP6 registers 0x00 6AA0 – 0x00 6ABF 32
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