Fundamentals-of-Microelectronics-Behzad-Razavi.pdf

32 if and what value of yields a collector current of

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32. If and , what value of yields a collector current of 1 mA in Fig. 5.129? Q 1 V CC = 2.5 V 20 k 1.6 k Figure 5.129 33. The topology depicted in Fig. 5.130(a) is called a “ multiplier.”(The counterpart has a similar topology.) Constructing the circuit shown in Fig. 5.130(b), determine the collector- Q 1 R 1 R 2 Q 1 R 1 R 2 V CC R 3 (a) (b) Figure 5.130
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 268 (1) 268 Chap. 5 Bipolar Amplifiers emitter voltage of if the base current is negligible. (The counterpart can also be used.) 34. We wish to design the CE stage of Fig. 5.131 for a voltage gain of 20. What is the minimum V CC Q 1 out V in V = 2.5 V 50 k Figure 5.131 allowable supply voltage if must remain in the active mode? Assume and V. 35. The circuit of Fig. 5.132 must be designed for maximum voltage gain while maintaining V CC Q 1 out V in V R C 1 k Figure 5.132 in the active mode. If V and V, calculate the required bias current. 36. The CE stage of Fig. 5.133 employs an ideal current source as the load. If the voltage gain V CC Q 1 out V in V Ideal Figure 5.133 is equal to 50 and the output impedance equal to 10 k , determine the bias current of the transistor. 37. Suppose the bipolar transistor in Fig. 5.134 exhibits the following hypothetical characteris- V CC Q 1 out V in V R C 1 k Figure 5.134 tic: (5.368) and no Early effect. Compute the voltage gain for a bias current of 1 mA.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 269 (1) Sec. 5.5 Chapter Summary 269 38. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.135. Assume . Transistor in Figs. 5.135(d) and (e) operates in soft saturation. Q 1 out V in V Q V CC 2 Q 1 out V in V Q V CC 2 R 1 Q Q 1 2 V CC R C out V in V Q Q 1 2 V CC R C out V in V Q Q 1 2 V CC R C out V in V (c) (a) (b) (d) (e) Figure 5.135 39. Repeat Problem 38 with . 40. Consider Eq. (5.157) for the gain of a degenerated CE stage. Writing , we note that and hence the voltage gain vary if changes with the signal level. For the following two cases, determine the relative change in the gain if varies by 10%: (a) is nominally equal to 3; (b) is nominally equal to 7. The more constant gain in the second case translates to greater circuit linearity. 41. Express the voltage gain of the stage depicted in Fig. 5.136 in terms of the collector bias V CC Q 1 out V in V R C R E Figure 5.136 current, , and . If , what is the gain if the dc voltage drops across and are equal to and , respectively? 42. We wish to design the degenerated stage of Fig. 5.137 for a voltage gain of 10 with operating at the edge of saturation. Calculate the bias current and the value of if , A, and . Calculate the input impedance of the circuit. 43. Repeat Problem 42 for a voltage gain of 100. Explain why no solution exists. What is the maximum gain that can be achieved in this stage?
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 270 (1) 270 Chap. 5 Bipolar Amplifiers V CC Q 1 out V in V R C = 2.5 V 200 Figure 5.137 44. Construct the small-signal model of the CE stage shown in Fig. 5.43(a) and calculate the voltage gain. Assume .
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