Circle6 it is up to the master and slave devices to

circle6 It is up to the master and slave devices to know whether a
received byte is meaningful or not.
circle6 A device must discard the received byte in a “transmit only”
frame or generate a dummy byte for a “receive only” frame.
circle6 SPI does not have an acknowledgement mechanism to
confirm receipt of data.
circle6 SPI is better suited to applications in which devices transfer
data streams such as the communication between a “codec”
(coder-decoder) and a digital signal processor.
Reference : Introduction to Serial Peripheral Interface from Embedded Systems Design

SPI Bus – Signal Lines
The four typical SPI signals include:
Serial clock (SCLK)
- This signal is generated by the Master.
- Other signals in the transmission change based on the
timing of edges from this clock.
– Data is typically output from the transmitter during the
falling edge of SCK.
– Data is typically latched by the receiver during the rising
edge of SCK.
circle6 master data output, slave data input (MOSI)
- This line is the output from the Master to the slave.
- Transmits bit-by-bit synchronized with Master clock edges.

SPI Bus – Signal Lines
master data input, slave data output (MISO)
–
-This line is the output from all the slaves connected.
- Transmits bit-by-bit from the slave synchronized with Master clock
edges.
chip select (CS) or slave select (SS)
- This is a bank of signals where each line goes to individual
slaves in the system.
- One line is asserted at a time to enable communicate with
the corresponding slave.
– When this signal goes low, the slave will listen for SPI clock and
data signals.

Master connected to one slave

SPI Bus – Typical SPI Connection
Reference : AT25512 SPI Serial EEPROM from Atmel

Data Transmission
circle6 A typical hardware setup using two shift registers to form an
inter-chip circular buffer
circle6 the master first configures the clock, using a frequency less
than or equal to the maximum frequency the slave device
supports.
circle6 Such frequencies are commonly in the range of 1-70 MHz.
circle6 The master then pulls the slave select low for the desired chip
circle6 With the SPI interface you can communicate with a device
transmitting and receiving 8 bits of data at the same time and
it is suited to high speed streaming data transfers.

Data Transmission
During each SPI clock cycle, a full duplex data transmission
occurs:
circle6 the master sends a bit on the MOSI line; the slave reads it
from that same line
circle6 the slave sends a bit on the MISO line; the master reads it
from that same line
circle6 Not all transmissions require all four of these operations to be
meaningful but they do happen.

Basic Transmission Step-by-Step
circle6 The Master drives a particular SS line low to initiate
communication with the corresponding slave.
circle6 Once the selected SS is low, one edge (rising or falling) of
the SCLK signals the devices (Master and Slave) to toggle
the MOSI and MISO to the correct bit of data being
transmitted.