169 6 33 Sequential Sampling Mode Single Channel Timing 170 6 34 Simultaneous

169 6 33 sequential sampling mode single channel

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169 6-33 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 170 6-34 Simultaneous Sampling Mode Timing ....................................................................................... 171 6-35 McBSP Receive Timing ........................................................................................................ 175 6-36 McBSP Transmit Timing ....................................................................................................... 175 6-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 176 6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 177 6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 178 6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 179 6 List of Figures Copyright © 2007–2010, Texas Instruments Incorporated
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 List of Tables 2-1 F2833x Hardware Features .................................................................................................... 13 2-2 F2823x Hardware Features .................................................................................................... 14 2-3 Signal Descriptions ............................................................................................................... 24 3-1 Addresses of Flash Sectors in F28335/F28235 ............................................................................. 39 3-2 Addresses of Flash Sectors in F28334/F28234 .............................................................................. 39 3-3 Addresses of Flash Sectors in F28332/F28232 .............................................................................. 39 3-4 Handling Security Code Locations ............................................................................................. 40 3-5 Wait-states ........................................................................................................................ 41 3-6 Boot Mode Selection ............................................................................................................. 44 3-7 Peripheral Frame 0 Registers .................................................................................................. 49 3-8 Peripheral Frame 1 Registers .................................................................................................. 49 3-9 Peripheral Frame 2 Registers .................................................................................................. 50 3-10 Peripheral Frame 3 Registers .................................................................................................. 50 3-11 Device Emulation Registers ..................................................................................................... 51 3-12 PIE Peripheral Interrupts ....................................................................................................... 54 3-13 PIE Configuration and Control Registers ...................................................................................... 55 3-14 External Interrupt Registers ..................................................................................................... 56 3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 58 3-16 PLL Settings ...................................................................................................................... 60 3-17 CLKIN Divide Options ........................................................................................................... 60 3-18 Possible PLL Configuration Modes ............................................................................................ 61 3-19 Low-Power Modes ............................................................................................................... 63 4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 67 4-2 ePWM Control and Status Registers (Default Configuration in PF1) ...................................................... 69 4-3 ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible) ........................... 70 4-4 eCAP Control and Status Registers ........................................................................................... 74 4-5 eQEP Control and Status Registers ........................................................................................... 76 4-6 ADC Registers ................................................................................................................... 82 4-7 McBSP Register Summary ...................................................................................................... 86 4-8 3.3-V eCAN Transceivers ...................................................................................................... 88 4-9 CAN Register Map .............................................................................................................. 91 4-10 SCI-A Registers .................................................................................................................. 93 4-11 SCI-B Registers .................................................................................................................. 93 4-12 SCI-C Registers ................................................................................................................. 94 4-13 SPI-A Registers ................................................................................................................... 97 4-14 I2C-A Registers ................................................................................................................. 100 4-15 GPIO Registers ................................................................................................................. 102 4-16 GPIO-A Mux Peripheral Selection Matrix ................................................................................... 103 4-17 GPIO-B Mux Peripheral Selection Matrix ................................................................................... 104 4-18 GPIO-C Mux Peripheral Selection Matrix ................................................................................... 105 4-19 XINTF Configuration and Control Register Mapping ....................................................................... 108 5-1 TMS320x2833x, 2823x Peripheral Selection Guide ....................................................................... 111 6-1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 118 6-2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ................. 119 6-3 Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 120 6-4 Clocking and Nomenclature (150-MHz Devices) ........................................................................... 125 Copyright © 2007–2010, Texas Instruments Incorporated List of Tables 7
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 6-5 Clocking and Nomenclature (100-MHz Devices) ........................................................................... 125 6-6 Input Clock Frequency ......................................................................................................... 126 6-7 XCLKIN Timing Requirements – PLL Enabled ............................................................................. 126 6-8 XCLKIN Timing Requirements – PLL Disabled ............................................................................ 126 6-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 126 6-10 Power Management and Supervisory Circuit Solutions ...................................................................
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