A and s a b s gate 3 gate 2 gate 1 wire 1 wire 2 wire

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(A and S) A B S Gate 3 Gate 2 Gate 1 Wire 1 Wire 2 Wire 0 A B Y S 2 x 1 Mux ° Input Load (I.L.) A, B: I.L. (NAND) = 61 fF S: I.L. (INV) + I.L. (NAND) = 50 fF + 61 fF = 111 fF ° Load Dependent Delay (L.D.D.): Same as Gate 3 TAYlhf = 0.021 ns / fF TAYhlf = 0.020 ns / fF TBYlhf = 0.021 ns / fF TBYhlf = 0.020 ns / fF TSYlhf = 0.021 ns / fF TSYlhf = 0.020 ns / fF
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