// Illegal: (state + 1) type is int not enum type
ECE 571 Introduction to SystemVerilog
System tasks & methods for enumerated types
SystemVerilog provides several special system functions called methods to
iterate through the values in an enumerated type list
<enum_var>.first
// Return value of first member in enumerated
// list of var
<enum_var>.last
// Return value of last member in enumerated
// list of var
<enum_var>.next(<N>)
// Return value of next member in enumerated
// list.
If N provided return Nth next member
<enum_var>.prev(<N>)
// Return value of previous member in enumerated
// list.If N provided return Nth previous member
<enum_var>.num
// Return the number of labels in the enumerated
// list of var
<enum_var>.name
// Return string representation of label for
// value
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ECE 571 Introduction to SystemVerilog
Parameterized Types
module adder #(parameter type dtype = logic [0:0]) // default is 1-bit size
(
input dtype a, b,
output dtype sum
);
assign sum = a + b;
endmodule
module top (
input logic [15:0] a, b,
input logic [31:0] c, d,
output logic [15:0] r1,
output logic [31:0] r2
);
adder #(.dtype(logic [15:0])) i1 (a, b, r1); // 16 bit adder
adder #(.dtype(logic signed [31:0])) i2 (c, d, r2); // 32-bit signed adder
endmodule
Literal Values
Source material drawn from:
•
Mark F. and Roy K. ECE 571 lecture slides
•
SystemVerilog for Design, 2
nd
Edition
by Stuart Sutherland
32
ECE 571 Introduction to SystemVerilog
Enhanced Literal Values
Scalable.
Change SIZE and this code still
works...but not for all cases
'0
fill all bits with 0
'1
fill all bits with 1
'z
fill all bits with z
'x
fill all bits with x
Verilog:
SystemVerilog:
data = ~0
// one’s complement
data = -
1
// two’s complement
data = {SIZE{1'b1}}; // replication
Doesn’t work for all 1’s (ex: if SIZE >
64 -> Need to edit code)
…or resort to “tricks” instead
No “tricks” needed
ECE 571 Introduction to SystemVerilog
Type Casting
“Classic” Verilog
is loosely typed
Allows assignment
of value of one type to variable or net of
different type
Value is converted to new type (following rules in Verilog
standard) when it is assigned.
Typecasting is different - allows value in an expression
to
be converted (not just during an assignment).
Verilog-1995 didn't support type casting.
Verilog-2001 added cast for conversion between
signed
and
unsigned
types (using $
signed
and $
unsigned
).
SystemVerilog adds a cast operator (similar to C language
but different syntax to preserve compatibility with Verilog).
Static
and
Dynamic
casts (sometimes called compile-time and
run-time)
You can cast: type, size, and sign
33
ECE 571 Introduction to SystemVerilog
Static Type Casting
Cast operator
No run-time checking.
ECE 571 Introduction to SystemVerilog
Syntax:
Examples:
Dynamic Type Casting
Error checking (run-time):
Casting a real to an int when value of real is too large to be
represented as an int
Casting a value to an enumerated type when value doesn't exist in
legal set of values
Can be called as task (as above, left) which causes runtime error if
check fails or system function (as above, right) which returns status
value (1 if successful, 0 if fail)
34
