Effective Access Time Associative Lookup εtime unit Assume memory cycle time is

Effective access time associative lookup εtime unit

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Effective Access Time ° Associative Lookup = ε time unit ° Assume memory cycle time is 1 unit of time (e.g. 80-250ns) ° Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers 8.13 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition ° Hit ratio = α ° Effective Access Time (EAT) EAT = (1 + ε ) α + (2 + ε )(1 – α ) = 2 + ε α
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Shared Pages ° Shared code ± One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). ± Shared code must appear in same location in the logical address space of all processes ° Private code and data 8.14 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition ± Each process keeps a separate copy of the code and data ± The pages for the private code and data can appear anywhere in the logical address space
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Shared Pages Example 8.15 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition
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Hierarchical Page Tables ° Motivating example: ± 32 -bit address space with 4KB per page. ± Page table would contain 2^32/ 2^12= 1 million entries. ± Need a 4MB page table with contiguous space. ° 4 bytes per entry ± Can we divide this page table into smaller pieces? 8.16 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition ° Break up the logical address space into multiple page tables ± A simple technique is a two-level page table
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Two-Level Page-Table Scheme 8.17 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition
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Two-Level Paging Example ° A logical address (on 32-bit machine with 2K page size) is divided into: ± a page number consisting of 20 bits ± a page offset consisting of 12 bits ° Since the page table is paged, the page number is further divided into: ± a 10-bit page number ± a 10-bit page offset 8.18 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition ° Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page number page offset p i p 2 d 10 10 12
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Address-Translation Scheme 8.19 Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition
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