Chapter 05c - MSP430 ISA - Instructions

1 1 z srcxordst dst xor source with destination and 1

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1 1 0 z src.xor.dst dst XOR source with destination AND 1 1 1 1 0 z src.and.dst dst AND source with destination Status Register: • = bit affected, – = bit not affected, 0 = cleared, 1 = set, z = same as Z Double Operand Instructions The BIT, BIC, BIS, XOR, and AND instructions replaces the destination operand with the results of the source operand operating on the destination operand. These are bit-wise, logical instructions The BIC and BIS do not affect the status register.
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BYU CS/ECEn 124 Chapter 05c - MSP430 Instructions 7 Logical Register Instructions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9-bit Op-code b/w As D/S-Reg Mnemonic Op-code V N Z C Operation Description RRC 0 0 0 1 0 0 0 0 0 C MSB …LSB C Roll dst right through C SWPB 0 0 0 1 0 0 0 0 1 – – – – Swap bytes Swap bytes RRA 0 0 0 1 0 0 0 1 0 0 MSB MSB …LSB C Roll destination right SXT 0 0 0 1 0 0 0 1 1 0 z bit 7 bit 8…bit 15 Sign extend destination PUSH 0 0 0 1 0 0 1 0 0 – – – – SP-2 SP, src @SP Push source on stack Status Register: • = bit affected, – = bit not affected, 0 = cleared, 1 = set, z = same as Z Single Operand Instructions The RCC, SWPB, RRA, and SXT instructions operate on a single. These are bit-wise, logical instructions. The BIC and BIS do not affect the status register. The PUSH instruction decrement the stack pointer by 2 and stores the operand on the stack using the indirect addressing mode.
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BYU CS/ECEn 124 Chapter 05c - MSP430 Instructions 8
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  • Fall '08
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  • Machine code, BYU CS/ECEn

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