# 50 the integrator of fig 829c must operate with

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50. The integrator of Fig. 8.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV. Determine the required values of and if pF. 51. Explain why dc offsets are not considered a serious issue in differentiators. 52. Explain the effect of op amp offset on the output of a logarithmic amplifier. 53. Suppose the input bias currents in Fig. 8.31 incur a small offset, i.e., . Calculate . 54. Repeat Problem 53 for the circuit shown in Fig. 8.33. What is the maximum allowable value of if the output error due to this mismatch must remain below a certain value, ? 55. A noninverting amplifier must provide a bandwidth of 100 MHz with a nominal gain of 4. Determine which one of the following op amp specifications are adequate: (a) , Hz. (a) , MHz. 56. An inverting amplifier incorporates an op amp whose frequency response is given by Eq. (8.84). Determine the transfer function of the closed-loop circuit and compute the bandwidth. 57. Figure 8.64 shows an integrator employing an op amp whose frequency response is given by (8.114)

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 416 (1) 416 Chap. 8 Operational Amplifier As A Black Box Determine the transfer function of the overall integrator. Simplify the result if . out V C 1 R 1 in V A ( ( s Figure 8.64 58. A noninverting amplifier with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0.5 V. If the op amp provides a slew rate of 1 V/ns, what is the highest input frequency for which no slewing occurs? 59. The unity-gain buffer of Fig. 8.3 must be designed to drive a 100 load with a gain error of . Determine the required op amp gain if the op amp has an output resistance of 1 k . Design Problems 60. Design a noninverting amplifier with a nominal gain of 4, a gain error of , and a total resistance of 20 k . Assume the op amp has a finite gain but is otherwise ideal. 61. Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 8 and a gain error of . Assume . 62. Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz. Assume the largest available capacitor is 50 pF. 63. With a finite op amp gain, the step response of an integrator is a slow exponential rather than an ideal ramp. Design an integrator whose step response approximates with an error less than for the range (Fig. 8.65). Assume , t out V V V 0 = 0.1% V V 0 Ideal Ramp Figure 8.65 V, and the capacitor must remain below 20 pF. 64. A voltage adder must realize the following function: , where and . Design the circuit if the worst-case error in or must remain below and the input impedance seen by or must exceed 10 k . 65. Design a logarithmic amplifier that “compresses” an input range of to an output range of . 66. Can a logarithmic amplifier be designed to have a small-signal gain ( ) of 2 at V and 0.2 at V? Assume the gain of the op amp is sufficiently high.
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