The idea of combining nmos and pmos current mirrors

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The idea of combining NMOS and PMOS current mirrors follows the bipolar counterpart depicted in Fig. 9.34. The circuit of Fig. 9.38 exemplifies these ideas. I V REF M REF V V V DD V V V in1 V out1 V DD V V in2 out2 in3 out3 in4 out4 DD CS Stage Follower Follower CS Stage Figure 9.38 NMOS and PMOS current mirrors in a typical circuit. 9.3 Chapter Summary Stacking a transistor atop another forms a cascode structure, resulting in a high output impedance. The cascode topology can also be considered an extreme case of source or emitter degener- ation. In deep-submicron CMOS technologies, the gate oxide thickness is reduced to less than 30 , leading to “tunneling” and hence noticeable gate current. This effect is beyond the scope of this book.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 449 (1) Sec. 9.3 Chapter Summary 449 The voltage gain of an amplifier can be expressed as , where denotes the short-circuit transconductance of the amplifier. This relationship indicates that the gain of amplifiers can be maximized by maximing their output impedance. With its high output impedance, a cascode stage can operate as a high-gain amplifier. The load of a cascode stage is also realized as a cascode circuit so as to approach an ideal current source. Setting the bias currents of analog circuits to well-defined values is difficult. For example, resistive dividers tied to the base or gate of transistors result in supply- and temperature- dependent currents. If or are well-defined, then or are not. Current mirrors can “copy” a well-defined reference current numerous times for various blocks in an analog system. Current mirrors can scale a reference current by integer or non-integer factors. Current mirrors are rarely used in disrcete design as their accuracy depends on matching between transistors. Problems 1. In the bipolar cascode stage of Fig. 9.2(a), A and for both transistors. Neglect the Early effect. (a) Compute for a bias current of 1 mA. (b) Noting that , determine the value of such that experiences a base-collector forward bias of only 300 mV. 2. Consider the cascode stage depicted in Fig. 9.39, where V. V Q 1 V Q 2 b1 b2 V R V CC 1 C Figure 9.39 (a) Repeat Problem 1 for this circuit, assuming a bias current of 0.5 mA. (b) With the minimum allowable value of , compute the maximum allowable value of such that experiences a base-collector forward bias of no more than 300 mV. 3. In the circuit of Fig. 9.39, we have chosen k and V. Estimate the maximum allowable bias current if each transistor sustains a base-collector forward bias of 200 mV. 4. Due to a manufacturing error, a parasitic resistor has appeared in the cascode circuits of Fig. 9.40. Determine the output resistance in each case. 5. Repeat Example 9.1 for the circuit shown in Fig. 9.41, assuming is ideal and equal to 0.5 mA, i.e., mA while mA.
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