We refer to the components that have full control of the system address lines

We refer to the components that have full control of

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We refer to the components that have full control of the system address lines as master components and the remaining blocks that do not facilitate transfers on the databus as accelerator components. The system bus has three segments—an interrupt bus, a data bus, and power control lines. The accelerators respond to read or write requests from the master side of the data bus, thus allowing the masters to read information content and control exe- cution of the accelerators. The two master devices consist of the event processor, comprising a small state machine, and an infrequently-used general-purpose microcontroller. A key benefit of the modular design of the architecture is its ability to employ fine-grained power management of individual components (both masters and accelerators). Selectively turning off components and using VDD-gating enables the system to minimize leakage power. For exam- ple, the general-purpose microcontroller core could be rel- atively complex and power-hungry when active, but can be VDD-gated most of the time when idle. The event proces- sor handles all interrupts, distributes tasks to accelerator devices, and wakes up the microcontroller only when nec- essary (rarely). J. Low Power Electronics 4, 1–10, 2008 7
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Survey of Hardware Systems for Wireless Sensor Networks Hempstead et al. We now describe some of the more interesting system components in greater detail. System Bus. The system bus comprises the data bus, the interrupt bus, and power control lines. The data bus has address, data, and control signals indicating read and write operations. Microcontroller. The microcontroller block is a sim- ple general-purpose CPU that implements the z80 instruc- tion set. Rather than designing this core from scratch, we modified an existing core to serve as the general-purpose compute element. The microcontroller is used to handle irregular events. Event Processor. The event processor (EP) is a pro- grammable state-machine that can process basic data transfers and power management instructions. This com- ponent orchestrates all of the other components’ tasks. It performs no computation, but executes Interrupt Ser- vice Routines (ISR) that transfer data between blocks and initializes accelerator components (or the general-purpose processor) to perform computation and service inter- rupts. The interrupt service routines also contain power- management instructions that allow the EP to explicitly perform fine-grained power management of all other sys- tem components. Interrupt Controller. The interrupt controller selects one of the interrupt lines for service. It provides simple priority selection and the ability to mask interrupts. Timer Subsystem. The periodic nature of sensor net- work applications requires multiple, configurable timers.
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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