4294 the predictor should be an n bit shift register

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4.29.4 The predictor should be an N-bit shiftregister, where N is the number of branch outcomes in the target pattern. The shiftregister should be initialized with the pattern itself (0 for NT, 1 for T), and the prediction is always the value in the leftmost bit of the shiftregister. The register should be shifted after each predicted branch. 4.29.5 Since the predictor’s output is always the opposite of the actual outcome of the branch instruction, the accuracy is zero. 4.29.6 The predictor is the same as in part d, except that it should compare its prediction to the actual outcome and invert (logical NOT) all the bits in the shiftregister if the prediction is incorrect. This predictor still always perfectly predicts the given pattern. For the opposite pattern, the first prediction will be incorrect, so the predictor’s state is inverted and after that the predictions are always correct. Overall, there is no warm-up period for the given pattern, and the warm-up period for the opposite pattern is only one branch.
Chapter 4 Solutions S-174.304.30.1 4.30.2 The Mux that selects the next PC must have inputs added to it. Each input is a constant address of an exception handler. The exception detectors must be added to the appropriate pipeline stage and the outputs of these detectors must be used to control the pre-PC Mux, and also to convert to NOPs instructions that are already in the pipeline behind the exception-triggering instruction. 4.30.3 Instructions are fetched normally until the exception is detected. When the exception is detected, all instructions that are in the pipeline after the first instruction must be converted to NOPs. As a result, the second instruction never completes and does not affect pipeline state. In the cycle that immediately follows the cycle in which the exception is detected, the processor will fetch the first instruction of the exception handler. 4.30.4 This approach requires us to fetch the address of the handler from memory. We must add the code of the exception to the address of the exception vector table, read the handler’s address from memory, and jump to that address. One way of doing this is to handle it like a special instruction that puts the address in EX, loads the handler’s address in MEM, and sets the PC in WB. 4.30.5 We need a special instruction that allows us to move a value from the (exception) Cause register to a general-purpose register. We must first save the general-purpose register (so we can restore it later), load the Cause register into it, add the address of the vector table to it, use the result as an address for a load that gets the address of the right exception handler from memory, and finally jump to that handler.
4.314.31.1 1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MOV X5, XZR IF ID EX ME WB B ENT IF ID EX ME WB CMP X5, X6 IF ID EX ME WB <not filled> B.NE TOP IF .. ID EX ME WB <not filled> LSL X10, X5, #3 .. IF ID EX ME WB <not filled> ADD X11, X1, X10 IF ID EX ME WB <not filled> LDUR X12, [X11, #0] IF ID EX ME WB <not filled> LDUR X13, [X11, #8] IF ID EX ME WB <not filled>

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