Sequential consistency lamport 1979 processors

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Sequential Consistency [Lamport 1979] Processors treated as if they are interleaved processes on a single time-shared CPU All references must fit into a total global order or interleaving that does not violate any CPUs program order Otherwise sequential consistency not maintained Now Dekker’s algorithm will work Appears to preclude any OOO memory references Hence precludes any real benefit from OOO CPUs
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High-Performance Sequential Consistency Coherent caches isolate CPUs if no sharing is occurring Absence of coherence activity means CPU is free to reorder references Still have to order references with respect to misses and other coherence activity (snoops) Key: use speculation Reorder references speculatively Track which addresses were touched speculatively Force replay (in order execution) of such references that collide with coherence activity
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Constraint graph example - SC Proc 1 ST A Proc 2 LD A ST B LD B Program order Program order WAR RAW Cycle indicates that execution is  incorrect 1. 2. 3. 4.
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Anatomy of a cycle Proc 1 ST A Proc 2 LD A ST B LD B Program order Program order WAR RAW Incoming invalidate Cache miss
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High-Performance Sequential Consistency Load queue records all speculative loads Bus writes/upgrades are checked against LQ Any matching load gets marked for replay At commit, loads are checked and replayed if necessary Results in machine flush, since load-dependent ops must also replay Practically, conflicts are rare, so expensive flush is OK
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Relaxed Consistency Models Key insight: only synchronizing references need ordering Hence, relax memory for all references Enable high-performance OOO implementation Require programmer to label synchronization references Hardware must carefully order these labeled references All other references can be performed out of order Labeling schemes: Explicit synchronization ops (acquire/release) Memory fence or memory barrier ops: All preceding ops must finish before following ones begin Often: fence ops cause pipeline drain in modern OOO machine More: ECE/CS 757
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Coherent Memory Interface
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Split Transaction Bus “Packet switched” vs. “circuit switched” Release bus after request issued Allow multiple concurrent requests to overlap memory latency Complicates control, arbitration, and coherence protocol Transient states for pending blocks (e.g. “req. issued but not completed”)
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Example: MSI (SGI-Origin-like, directory, invalidate) High Level
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Example: MSI (SGI-Origin-like, directory, invalidate) High Level Busy States
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Example: MSI (SGI-Origin-like, directory, invalidate) High Level Busy States Races
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Multithreading Basic idea: CPU resources are expensive and should not be left idle 1960’s: Virtual memory and multiprogramming VM/MP invented to tolerate latency to secondary storage (disk/tape/etc.) Processor:secondary storage cycle-time ratio: microseconds to tens of
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  • Fall '09
  • PROFGURISOHI
  • Central processing unit, CPU cache, thread-level parallelism

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