38Clocked-Scan CellSCKQ/SODISIDCKClocked-scan cellIn the clocked-scan cell, input selection is conducted using two independent clocks, DCKand SCK.
EE141VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P. 39Clocked-Scan CellClocked-scan cell design and operationIn normal/capture mode, the data clock DCKis used to capture the contentspresent at the data input DI into the clocked-scan cell. In shift mode, the shiftclock SCK is used to shift in new data from the scan input SI into the clocked -scan cell, while the content of the clocked-scan cell is being shifted out.
EE141VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P. 40LSSD Scan Cell+L2CD....AI....B+L1L1L2SRLPolarity-hold SRL (shift register latch)An LSSD scan cell is used for level-sensitivelatch base designs.This scan cell contains two latches, a master 2-port D latch L1and a slave D latch L2. Clocks C,A and B are used to select between the data input D and the scan input I to drive +L1and +L2. In an LSSD design, either +L1or +L2can be used to drive the combinational logic of the design.
EE141VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P. 41LSSD Scan CellCDI+L1D1D2D3D4T1T2T3T4D1T3AB+L2T3Polarity-hold SRL design and operationIn order to guarantee race-free operation, clocks A, B, and C are applied in a non-overlapping manner.The master latch L1uses the system clock C to latch system data from the data input D and to output this data onto +L1. Clock B is used after clock A to latch the system data from latch L1and to output this data onto +L2.
EE141VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P. 42Comparing three scan cell designsIncrease routing complexityInsert scan into a latch-based designGuarantee to be race-freeLSSD Scan CellRequire additional shift clock routingNo performance degradation Clocked-Scan CellAdd a multiplexer delayCompatibility to modern designsComprehensive support provided by existing design automation toolsMuxed-D Scan CellDisadvantagesAdvantages
EE14143VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P. 43Scan ArchitecturesScan ArchitecturesboxshadowdwnFull-Scan Designsquare4All or almost all storage element are converted into scan cells and combinational ATPG is used for test generationboxshadowdwnPartial-Scan Designsquare4A subset of storage elements are converted into scan cells and sequential ATPG is typically used for test generationboxshadowdwnRandom-Access Scan Designsquare4A random addressing mechanism, instead of serial scan chains, is used to provide direct access to read or write any scan cell
EE141VLSI Test Principles and ArchitecturesCh. 2 - Design for Testability - P.