The wait may be long the host should probably switch

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# The wait may be long, the host should probably switch to another task. # Interrupt : the hardware mechanism that enables a device to notify the CPU when it is ready for service. 14 Interrupt Mechanism ! The CPU hardware has a wire called the interrupt-request line that the CPU senses after executing every instruction. ! When the CPU detects that a controller has asserted a signal on the line, the CPU performs a state save and transfers control to a generic routine. ! The generic routine examine the interrupt information and calls the interrupt-specific handler. " Polling all the devices to see which one raised the interrupt. ! Ideally, interrupts must be handled quickly (data overflow on keyboard controller) . " Fortunately, only a predefined number of interrupts is possible. " The modern interrupt mechanism accepts an address (index) in accordance with a interrupt vector (table) to provide fast interrupt service.
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Introduction to OS 8 15 Interrupt Mechanism (cont’d) ! The interrupt vector contains the addresses of all the specific interrupt handle routines. ! The address (index) is an offset in the interrupt vector. ! This vectored interrupt mechanism can reduce the need for a single interrupt handler to search all possible sources of interrupts. ! Operating systems as different as Windows and Unix dispatch interrupt in this manner. The design of the interrupt vector for the Intel Pentium processor. Used for device-generated interrupts 16 Interrupt Mechanism (cont’d) ! The interrupt mechanism must also save the address of the interrupted instruction. " It may also save the state (processor register values). ! After the interrupt is serviced, the saved address (and saved state) is loaded, and the interrupted computation resumes as though the interrupt had not occurred. ! Note: " Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt . " A trap is a software-generated interrupt caused either by an error or a user request (system call).
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Introduction to OS 9 17 Interrupt Timeline 18 Example of Interrupt P 1 I/O operations (read) I/O device P 2 Interrupt handler time I/O devices and the CPU can execute concurrently Point of interruption I/O ready to transfer data Send an interrupt signal to CPU to indicate that it is ready Resume the interrupted process Time sharing (or multitasking)
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Introduction to OS 10 19 Storage Structure ! Main memory and the registers are the only storage that the CPU can access directly. ! Registers: " Are built into the CPU. " CPU can decode instructions and perform simple operations on register contents. ! Main memory: " Computer programs must be in main memory to be executed. " Is the only large storage area that the CPU can access directly. 20 Storage Structure (cont’d) ! A typical (instruction) execution cycle first fetches an instruction from memory.
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  • Spring '12
  • GwangS.Jung
  • OS, main memory

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