EEE6323S12-HLec04-DCTransient-4spp

3 input nand caps annotate the 3 input nand gate with

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3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 3C 3C 3C 3C 2C 2C 2C 2C 2C 2C 3C 3C 3C 2C 2C 2C Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder R 1 R 2 R 3 R N C 1 C 2 C 3 C N
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6 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 2 2 2 2 B A x Y Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 2 2 2 2 B A x Y Delay Components Delay has two parts Parasitic delay Effort delay Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously 6C 2C 2 2 2 2 4hC B A x Y
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7 Pin Reordering A and B transition High – If A arrives earlier than B 6C 2C 2 2 2 2 4hC B A x Y Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact 3C 2C 2C 3C 3C Isolated Contacted Diffusion Merged Uncontacted Diffusion Shared Contacted Diffusion 3 3 3 2 2 2 A V DD GND B Y A V DD GND B Y Which Layout is better?
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