lect15-adv-microarchitecture

Wakeup select select 2 3 wakeup 5 6 select 4 5 wakeup

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Wakeup / select Select 2, 3 Wakeup 5, 6 Select 4, 5 Wakeup 6 Select 6 Ready inst to issue 1 2, 3, 4 4, 5 6 1 2 3 4 5 6
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Scheduling Atomicity Operations in the scheduling loop must occur within a  single clock cycle For back-to-back execution of dependent instructions n n+1 n+2 n+3 n+4 select 1 wakeup 2, 3 select 2, 3 wakeup 4 select 4 select 1 wakeup 2, 3 Select 2, 3 wakeup 4 Select 4 Atomic scheduling Non-Atomic 2-cycle scheduling cycle 1 4 1 2 3 4 2 3
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Implication of scheduling atomicity Pipelining is a standard way to improve clock  frequency Hard to pipeline instruction scheduling logic  without losing ILP ~10% IPC loss in 2-cycle scheduling ~19% IPC loss in 3-cycle scheduling A major obstacle to building high-frequency  microprocessors
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Scheduler Designs Data-Capture Scheduler keep the most recent  register value in  reservation stations Data forwarding and  wakeup are combined Register File Data-captured scheduling window (reservation station) Functional Units Forwarding and wakeup Register update
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Scheduler Designs Non-Data-Capture  Scheduler keep the most recent  register value in RF  (physical registers) Data forwarding and  wakeup are decoupled Register File Non-data-capture scheduling window Functional Units Forwarding wakeup Complexity benefits simpler scheduler / data / wakeup path
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Mapping to pipeline stages AMD K7 (data-capture) Pentium 4 (non-data-capture) Data Data Data / wakeup wakeup
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Scheduling atomicity  & non-data-capture scheduler Fetch Decode Sched /Exe Writeback Commit Atomic Sched/Exe Schedule Dispatch Writeback Commit wakeup/ select RF Exe Wakeup /Select Multi-cycle scheduling loop Scheduling atomicity is not maintained Separated by extra pipeline stages (Disp, RF) Unable to issue dependent instructions consecutively  solution:  speculative scheduling
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Speculative Scheduling Speculatively wakeup dependent instructions even before the  parent instruction starts execution Keep the scheduling loop within a single clock cycle But, nobody knows what will happen in the future Source of uncertainty in instruction scheduling: loads Cache hit / miss Store-to-load aliasing  eventually affects timing decisions Scheduler assumes that all types of instructions have pre- determined fixed latencies Load instructions are assumed to have a common case (over 90% in  general) $DL1 hit latency If incorrect, subsequent (dependent) instructions are replayed
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Speculative Scheduling Overview Spec wakeup /select Fetch Decode Schedule Dispatch Writeback /Recover Commit Speculatively issued instructions Re-schedule when latency mispredicted RF Latency Changed!!
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  • Fall '09
  • PROFGURISOHI
  • wavefront, instruction scheduling, scheduling – scheduling, iCFP, scheduling window wakeup, dependent instructions

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