CECS 341 Computer Architecture © 2018R. W. Allison Instruction Set Architecture – Page 6 D.Instruction Sets (cont.)The goal of the RISC architecture is high throughput and fast execution of simple instructions. To achieve these goals, accesses to memory, which typically take longer than elementary operations, are to be avoided, except for fetching instructions. A result of this methodology is the need for a relatively large register file (as mentioned earlier) to hold the operands -- all instructions besides load and store are register based. Because of the fixed instruction length, limited addressing modes, and elementary operations, the control unit of a RISC is comparatively simple and is typically "hardwired." In addition, the underlying organization is universally a pipeline design. The goal of the CISC architecture is to match more closely the operations used in programming languages and to provide instructions that facilitate compact programs and conserve memory. In addition, efficiencies in performance may result through the reduced number of instruction fetches from memory (less overhead), compared to the number of elementary operations performed. Because of the accessibility of memory as operands for most operations, the register files in CISC are smaller than in RISC. In addition, because of the complexity of instructions and the variability of the instruction formats, "microprogrammed" control units are often employed. In the quest for speed, the microprogrammed control in newer designs (e.g. Pentium processors) is controlling a pipelined datapath. In fact, the AMD series of processors that emulate the Pentium instruction sets actually convert the CISC instructions to an internal sequence of RISC-like operations that are processed in a RISC pipeline.