At end of count the interrupt request line IRQ4 or IRQ5 clocks a toggle flip

At end of count the interrupt request line irq4 or

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At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a toggle flip-flop. The output of this flip-flop drives the T OUT line, P36. In all cases, when the selected counter/timer reaches its end-of-count, T OUT toggles to its opposite state (Figure 6-11). If, for example, the counter/timer is in Continuous Counting Mode, Tout will have a 50 percent duty cycle output. This duty cycle can easily be controlled by varying the initial values after each end-of-count. The internal clock can be selected as output instead of T0 or T1 by setting TMR bit 7 and bit 6 both to 1. The internal clock (XTAL frequency/2) is then directly output on P36 (Figure 6-12). While programmed as T OUT , P36 cannot be modified by a write to port register P3. However, the Z8 ® software can examine the P36 current output by reading the port regis- ter. Figure 6-11. T0 and T1 Output Through T OUT ÷ 2 P3 6 T OUT TMR D 7 - D 6 = 01 IRQ 4 (T0 End-of-Count) IRQ 5 (T1 End-of-Count) TMR D 7 - D 6 = 10 Figure 6-12. Internal Clock Output Through T OUT OSC ÷ 2 P3 6 T OUT Internal TMR D 6 Clock TMR D 7
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Z8 Microcontrollers ZiLOG Counter/Timers UM001600-Z8X0599 6-7 6.5 T IN MODES The Timer Mode Register TMR (F1H) (Figure 6-13) is used in conjunction with the Prescaler Register PRE1 (F3H) (Figure 6-14) to configure P31 as T IN . T IN is used in con- junction with T1 in one of four modes: External Clock Input Gated Internal Clock Triggered Internal Clock Retriggerable Internal Clock Note: The T IN mode is restricted for use with timer 1 only. To enable the T IN mode selected (via TMR bits 4- 5), bit 1 of PRE1 must be set to 0. The counter/timer clock source must be configured for ex- ternal by setting the PRE1 Register bit 2 to 1. The Timer Mode Register bit 5 and bit 4 can then be used to select the desired T IN operation. For T1 to start counting as a result of a T IN input, the En- able Count bit (bit 3 in TMR) must be set to 1. When using T IN as an external clock or a gate input, the initial values must be loaded into the down counters by setting the Load bit (bit 2 in TMR) to a 1 before counting begins. In the de- scriptions of T IN that follow, it is assumed the programmer has performed these operations. Initial values are auto- matically loaded in Trigger and Retrigger modes so soft- ware loading is unnecessary. Figure 6-13. Timer Mode Register (T IN Operation) D5 D4 (Read/Write) Timer Mode Register (TMR) Register F1H (Retriggerable) (Non-retriggerable) Trigger Input = 10 T IN = Modes: External Clock Input = 00 Gate Input = 01 Trigger Input = 11 Figure 6-14. Prescaler 1 Register (T IN Operation) D7 D6 D5 D4 D3 D2 D1 D0 (Write-Only) 1 = T 1 Internal Disable T IN Mode Clock Source 0 = T 1 External Enable T IN Mode Prescaler 1 Register (PRE1) Register F3H
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Z8 Microcontrollers Counter/Timers ZiLOG 6-8 UM001600-Z8X0599 It is suggested that P31 be configured as an input line by setting P3M Register bit 5 to 0, although T IN is still function- al if P31 is configured as a handshake input.
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  • Summer '17
  • ericsson
  • ........., Interrupt, Interrupt request, Programmable Interrupt Controller, Zilog

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