EEL6323S12-HLec05-LogicalEffort-4spp

# Assume now that an inverter template has the

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Assume now that an inverter template has the following R INV : Pull-up and pull-down resistance C INV : Input capacitance Multiply and divide by R inv C inv Delay in a Logic Gate Express delays in terms of process-independent unit d abs = d τ Logical Effort Logical Effort Captures the properties of the gate topology on it s ability to produce current Measure of how much more input capacitance a gate must present to deliver the same output current as an inverter Defined such that an inverter has logical effort of 1 d = f + p = gh + p

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3 Computing Logical Effort DEF: of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs. fanout plots Or estimate by counting transistor widths A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Logical Effort Use delay versus fanout curves Slope of lines is the logical effort ElectricalEffort: h = C out / C in NormalizedDelay:d Inverter 2-input NAND g = p = d = g = p = d = EffortDelay:f Parasitic Delay: p 0 1 2 3 4 5 0 1 2 3 4 5 6 d = f + p = gh + p Catalog of Gates
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• Spring '10
• bashir
• Transistor, Logic gate, logical effort

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