H copies 6c 2c 2 2 2 2 4hc b a x y digital ic slide

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h copies 6C 2C 2 2 2 2 4hC B A x Y
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Digital IC Slide 42 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y pdr t
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Digital IC Slide 43 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y RC h t pdr ) 4 6 ( 2 ln
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Digital IC Slide 44 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y
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Digital IC Slide 45 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y pdf t (6+4h)C 2C R/2 R/2 x Y
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Digital IC Slide 46 Example: 2-input NAND Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y (6+4h)C 2C R/2 R/2 x Y RC h R R C h R C t pdf ) 4 7 ( 2 ln ) 2 2 ]( ) 4 6 [( 2 2 2 ln
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Digital IC Slide 47 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance
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Digital IC Slide 48 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y R 3 2 cdr t h RC
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Digital IC 7C 3C 3C 3 3 3 2 2 2 3C 2C 2C 3C 3C Isolated Contacted Diffusion Merged Uncontacted Diffusion Shared Contacted Diffusion we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Slide 49 Diffusion Capacitance
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Digital IC Slide 50 Layout Comparison Which layout is better? A V DD GND B Y A V DD GND B Y
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Digital IC 51 Transistor Sizing C L B R n A R p B R p A R n C int B R p A R p A R n B R n C L C int 2 2 2 2 1 1 4 4
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Digital IC 52 Transistor Sizing a Complex CMOS Gate OUT = D + A • (B + C) D A B C D A B C 1 2 2 2 4 4 8 8 6 3 6 6
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Digital IC 53 Fan-In Considerations D C B A D C B A C L C 3 C 2 C 1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case.
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Digital IC 54 t p as a function of fan-in t pL H t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided 0 250 500 750 1000 1250 2 4 6 8 10 12 14 16 t pHL quadratic linear t p
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