{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

See references for fft processor e c leuthardt g

Info iconThis preview shows pages 4–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: See references for FFT Processor E. C. Leuthardt, G. Schalk, J. R. Wolpaw, J. G. Ojemann, and D. W. Moran, " A brain-computer interface using electrocorticographic signals in humans," J. Neural Eng., vol.1, no.2, pp. 63-71, 2004. K. J. Miller, E. C. Leuthardt, G. Schalk, R. P. N. Rao, N. R. Anderson, D. W. Moran, J. W. Miller, and J. G. Ojemann, "Spectral changes in cortical surface potentials during motor movement," J. Neurosci., vol. 27, no. 9, pp. 2424-2432, 2007. 7. A high speed ADC backend For this project, a digital backend of a high speed flash ADC is implemented. The desired sample rate is 4GSamples/s, and the nominal resolution is 5 bits. Due to the extremely high throughput (20Gb/s), it’s impossible to test the ADC in real time at reasonable costs. There are two workarounds. The first is to decimate the ADC output until the data rate is within the equipment limit. The other is to store the data in a memory (shown as FIFO in the block diagram) and later read them for offline post-processing. Both approaches need to be implemented in this project. The design goal is to high throughput to process the sampled data. Timeline Date Description Points 03/26 Project Assigned 03/28 Form groups (5 students per group) Brainstorming Phase: Determine the topic and carry out literature review 04/02 Submission of Project topic (1 page description) 5 pts 03/28- 04/9 Design and Analysis Phase: Simulation, design and analysis. 04/9- 04/19 Physical Implementation Phase: Layout and I/O Ring with full chip DRC and LVS 04/22 By Noon Report: 4 – page paper 100 pts 04/23 Final Project report demo/presentation 10:00am 2nd floor Comp. Lab Important Dates: • April 02, 2013: Submit your design topic. ( 5 pts ). • April 22, 2013: Paper due along with LVS and DRC report. • April 23, 2013: Project check off. ( 100pts ) Report As general guidelines, try to first understand the specifications before design implementation. Use HDL (Verilog-HDL/VHDL) as the design input . Go through the basic steps of general VLSI design flow (From HDL to GDS) . You will need to hand in both a soft copy and hard copy of your source code: 1. Hand in HDL source code, result of each step, design report. 2. Design description, implementation notes, simulation result and performance summary (Power, area and speed etc) should be mentioned in this design report. 3. Submit your DRC and LVS report without the pads. If you have the DRC and LVS clean report with the IO pads also you get extra credit. 4. Write a 4- page double column paper in IEEE format. Download a word file template from: http://www.ieee.org/web/publications/authors/transjnl/index.html The paper should include Title, Author list (group members), Abstract, Introduction, a section describing design methodology, a section describing results and discussions, Conclusions and Reference list. All figures, including schematics waveform, plots and layout must be embedded within the paper. The paper cannot exceed four pages in length. Figures should be chosen appropriately to best explain the overall design and results....
View Full Document

{[ snackBarMessage ]}

Page4 / 5

See references for FFT Processor E C Leuthardt G Schalk J R...

This preview shows document pages 4 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon bookmark
Ask a homework question - tutors are online