ESC201A-Endsem_paper 2015.pdf

In fig2 initially 1 q q i write down the state 1 q q

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Problem3: [6.0 + 2.0] In Fig.2 initially 0 1 0 Q Q . (i) Write down the state 1 0 Q Q transition table for this sequential circuit. (ii) Find the logic state 1 0 Q Q immediately after th 777 clock pulse. Fig.2
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Problem4: [6.0 + 3.0] A 8 : 3 decoder as shown in Fig.3, has 3 inputs C B A , , and 8 output lines 7 , ..... , 0 D D with the property that for any inputs C B A , , the output on the line corresponding to the binary number ABC is 1 , while the rest are 0 . For instance, for 1 , 1 , 0 C B A , the output 3 D equals 1 , while the rest are zero. Fig.3 A combinational circuit has 3 outputs 2 , 1 F F and 3 F as follows: B A C B A F B A C B A F C A C B A F . . . 3 . . . 2 . . . 1 (i) Represent F 1, F 2, F 3 as the sum of minterms i.e. , , 2 1 n n m (ii) Design the circuit to generate 3 , 2 , 1 F F F with a 8 : 3 decoder and external gates. Probelm5: [6.0 + 2.0] For the circuit in Fig.4, the multiplexer output can be either V 0 or V 5 corresponding to the logical levels 0 and 1 respectively and the binary up counter is modulo 4. (i) Calculate the steady state maximum and minimum levels for ) ( t v o given a clock frequency of KHz 1 (ii) Sketch the voltages Y and ) ( t v o for a duration of ms 8 .
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