However, changing the clock frequency by a factor of k changes the amount of time it takes forthe operation to complete by a factor of 1/k. Since Energy = Power*Time, the net scaling inenergy/operation in the logic isk2.For the scaling above, the energy per operation becomes(1J+ 0.1(2)J)(18/20)2= 0.972Jcompared to1.2Jin the original.A more substantial energy efficiency improvement can be gained by pipelining the combina-tional logic. When pipelining, the critical path is reduced which allows the clock rate to beincreased without changingVdd. Since this application does not require a clock rate increase,the clock frequency andVddcan both be scaled down from the new clock frequency made pos-sible by pipe-lining. The total amount of time an operation take to get through the pipelinechanges to become the number of pipeline stages * the delay through each pipeline stage.This changes the energy/op scaling factor because power is scaled byk3but time/op is nowscaled byn/k. This leads to energy/op scaling bynk2.Let’s divide the combination logic into 2 equal parts (from the perspective of delay) and inserta pipeline register between them. We incur the additional energy use of the pipeline registerbut can now reduce the combinational logic delay to 8 ns. This leads to a critical path of 10ns. This allows clock frequency andVddto be scaled by a factor of1/2to reach the target clockfrequency of 50 MHz (20 ns period). The total energy per operation of this pipelined versionis(1J+ 0.1(3)J)(2)(1/2)2= 0.65J.This process can be tried again by splitting the combinational logic into n segments with n-1additional regsiters.Assuming the combinational logic is evenly split, the critical path when pipelined by an integerfactornis16/n+ 2ns. The energy/operation is(1 + 0.1(1 +n))((16/n+ 2)/20)2nTo find when the energy/op is minimum, we can take the first derivative of the above expressionand get0.027-0.704n-2-0.02nThe only real zero is atn≈4.431.The second derivative is:0.002 + 1.408n-3This is positive forn≈4.431identifyingn≈4.431as a local minimum.Since n must be an integer, we will look atn= 4andn= 5Version: 1 - 2019-04-10 19:32:31-07:00
EECS 151/251A Homework 711Forn= 4, the critical path delay is16/4 + 2 = 4/3ns. The energy/operation is(1 + 0.1(1 +4))((16/4 + 2)/20)2(4)≈0.54J.Forn= 5, the critical path delay is16/5 + 2 = 26/5ns. The energy/operation is(1 + 0.1(1 +5))((16/5 + 2)/20)2(5)≈0.5408J.Therefore, the minimum energy/operation is achieved for this circuit when pipelined by a factorof 4 yielding an energy/op of0.54J.