EEE6323S12-HLec04-DCTransient-4spp

# Dd b0 v dd v out 0 v in v dd v dd β n β p 1 a0 y 4w

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DD B=0 V DD V out 0 V in V DD V DD β n / β p = 1 A=0 Y 4W 4W W W VTC of complex gates Case 2: Assume A=0 V DD and B=0 V DD B=0 V DD V out 0 V in V DD V DD β n / β p = 1 Y 4W 4W W W A=0 V DD Duty Cycle Distortion How do Skewed gates effect duty-cycle? Where is this relevant? V out 0 V in V DD V DD β n / β p = 1 V TRIP1 V TRIP2 V in V out 50% duty cycle

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3 Noise Margins How much noise can a gate input see before it does not recognize the input? – N MH – N ML =V The image cannot be The image cannot be The image cannot be displayed. Your The image cannot be displayed. Your Indeterminate Region Input Characteristics Output Characteristics V OH V DD V OL GND V IH V IL Logical High Input Range Logical Low Input Range Logical High Output Range Logical Low Output Range Logic Levels To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic V DD V in V out V OH V DD V OL V IL V IH V tn Unity Gain Points Slope = -1 V DD - |V tp | β p / β n > 1 V in V out 0 Tradeoff between NM H and NM L Increasing NM H decreases NM L V OH1 V OL1 V IL1 V IH1 V IL2 V IH2 V OL2 V OH2 V OUT1 V IN1 V IN2 V OUT2 Delay Definitions t pdr (t pLH ) : rising propagation delay From input 50% to rising output 50% crossing t pdf (t pHL ) : falling propagation delay (t pHL ) From input 50% to falling output 50% crossing t pd : average propagation delay t cdr : rising contamination delay Minimum time from input 50% crossing to rising output crossing V DD /2
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• Spring '10
• bashir
• RC circuit, Electronics terms, propagation delay, logic level

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