# 1026a such a scenario maintains constant because eqs

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10.26(a), such a scenario maintains constant because Eqs. (10.27)-(10.32) apply to this case equally well. It follows that

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 491 (1) Sec. 10.3 MOS Differential Pair 491 R D M 1 I SS R D DD M 2 V X Y V CM V + V CM V P Figure 10.26 Response of MOS pair to small differential inputs. (10.114) (10.115) and (10.116) As expected, the differential voltage gain is given by (10.117) similar to that of a common-source stage. Example 10.16 Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1.6 V. Assume , , and V. Solution From the power budget and the supply voltage, we have (10.118) The output CM level (in the absence of signals) is equal to (10.119) For V, each resistor must sustain a voltage drop of no more than 200 mV, thereby assuming a maximum value of (10.120) Setting , we must choose the transistor dimensions such that . Since each transistor carries a drain current of , (10.121) and hence (10.122)
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 492 (1) 492 Chap. 10 Differential Amplifiers The large aspect ratio arises from the small drop allowed across the load resistors. Exercise If the aspect ratio must remain below 200, what voltage gain can be achieved? Example 10.17 What is the maximum allowable input CM level in the above example if V? Solution We rewrite (10.107) as (10.123) (10.124) This is conceptually illustrated in Fig. 10.27. Thus, R D M 1 I SS R D DD M 2 V X Y V CM,in V CM,in V V TH CM,out Figure 10.27 (10.125) Interestingly, the input CM level can comfortably remain at . In contrast to Example 10.5, the constraint on the load resistor in this case arises from the output CM level requirement. Exercise Does the above result hold if V. Example 10.18 The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load resistors. If the two circuits are designed for the same voltage gain and the same supply voltage, discuss the choice of (a) transistor dimensions for a given power budget, (b) power dissipation for given transistor dimensions. Solution (a) For the two circuits to consume the same amount of power ; i.e.,

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 493 (1) Sec. 10.3 MOS Differential Pair 493 R M 1 I SS R DD M 2 V V in1 V in2 M 1 V DD in v R Figure 10.28 each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. Equation (10.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. (b) If the transistors in both circuits have the same dimensions, then the tail current of the differential pair must be twice the bias current of the CS stage for - to have the same transconductance, doubling the power consumption.
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