Fundamentals-of-Microelectronics-Behzad-Razavi.pdf

Exercise how many time constants does the output take

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Exercise How many time constants does the output take to reach within 90% of its ideal value. The foregoing example reveals a fundamental limitation: in the presence of a load capacitance, a logical gate cannot respond immediately to an input. The circuit of Fig. 15.10(a) takes roughly three time constants to produce a reliable level at the output and, as such, suffers from a “delay.” That is, the speed of gates is limited by the finite transition time at the output and the resulting delay. Playing a critical role in high-speed digital design, the transition time and the delay must be defined carefully. As illustrated in Fig. 15.11(a), we define the output “risetime,” , as the time V DD 0 V DD t V DD 90% V DD 10% T R T F t V in out V V DD 2 T PLH T PHL (a) (b) Figure 15.11 Definition of (a) rise and fall times, and (b) propagation delays. required for the output to go from of to of . Similarly, the output “falltime,” This definition applies only if the low and high levels are equal to 0 and , respectively.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 785 (1) Sec. 15.1 General Considerations 785 , is defined as the time required for the output to go from of to of . In general, and may not be equal. Since the input to a gate is produced by another gate and hence suffers from a finite transition time, the delay of the gate must be characterized with a realistic input waveform rather than the abrupt step in Fig. 15.11(a). We therefore apply a step with a typical risetime at the input and define the propagation delay as the difference between the time points at which the input and the output cross [Fig. 15.11(b)]. Since the output rise and fall times may not be equal, a low-to-high delay, , and a high-to-low delay, , are necessary to characterize the speed. In today’s CMOS technology, gate delays as little as 10 ps can be obtained. The reader may wonder about the nature of the load capacitance in Example 15.9. If the gate drives only another stage on the chip, this capacitance arises from two sources: the input capacitance of the subsequent gate(s) and the capacitance associated with the “interconnect” (on-chip wire) that carries the signal from one circuit to another. Example 15.10 An NMOS inverter drives an identical stage as depicted in Fig. 15.12. We say the first gate sees a R M 1 D V in R M V DD D out V 2 X Figure 15.12 Cascade of inverters. “fanout” of unity. Assuming a degradation in the output low level (Example 15.8), determine the time constant at node when goes from low to high. Assume . Solution Recall from Example 15.9 that this time constant is simply equal to . Assuming , we write (15.23) (15.24) (15.25) Exercise Suppose the width of is doubled while remains unchanged. Calculate the time con- stant. Example 15.11 In Example 15.4, the wire connecting the output of to the input of exhibits a ca-
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 786 (1) 786 Chap. 15 Digital CMOS Circuits pacitance of F (50 aF) per micron of length. What is the interconnect capacitance driven by ?
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