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number of trials(extraction, delay calculation, and timing flow) to produce full circuit delay distributionAttractive properties:Considered very accurateand represent realityConceptually easy to implementWell understood by the designersDisadvantages:High computational cost•Number of trials is typically in the order of 5000-10000Using Monte-Carlo techniques in circuit optimization loop is difficult and has limitationChapter 5: Timing Analysis and Optimization5-57
Statistical Static Timing Analysis (SSTA)SSTA = STA + Statistical distributions of:Gate delays: Delay behavior of the gate at different values of the parameters influenced by process and operating conditionsInterconnect parasiticsOperating conditions: Uncertainty in environmental conditions during the operation of a chip (power supply, temperature, etc.)The distribution of gate delays (pdfor CDF) can be in any form: normal, uniform, etc...SSTA computes node and path delay distributionsand estimate the circuit delayas the joint distributionsThe distribution of circuit delayscan be represented by continuous or discrete functions(either pdfor CDF)Key difference between STA and SSTA: Single values versus distribution functionsChapter 5: Timing Analysis and Optimization5-58
Some FundamentalsChapter 5: Timing Analysis and Optimization 12221222;for ;11Shift:Scae:l1XxXXXXnXiXinXiXiXXiXXYXYXCDFFxP XxxdpdffxFxFxft dtdxmE Xxxfx dxnVAR Xxmxmfx dxnEXE XSTD XYXafyfyayYaXfyfaa 5-59
Chapter 5: Timing Analysis and Optimization22Joint Joint If and are independent the,,,;,,:,,nXYyxXYXYXYXYXYXYXYXYXYXYXYXFx yPXxYyfx yFx yFx yfd dx yFx yPXxYyPXxPYyFx Fyddfx yFx FyFxFyfxx ydxdCDFpdyfXY Yfy222221:( );;2121:;(,Uniform distrib)utionGaussian (Normal)2XXXXXxmXXfxaxbbaabbamE XVAR Xfxex 5-60