number of trials
(extraction, delay calculation, and timing flow)
to produce full circuit delay distribution
Attractive properties:
Considered
very accurate
and represent reality
Conceptually easy to implement
Well understood by the designers
Disadvantages:
High computational cost
•
Number of trials is typically in the order of 5000-10000
Using Monte-Carlo techniques in circuit optimization loop is difficult and
has limitation
Chapter 5: Timing Analysis and Optimization
5-57

Statistical Static Timing Analysis (SSTA)
SSTA = STA + Statistical distributions of:
Gate delays
: Delay behavior of the gate at different values of the
parameters influenced by process and operating conditions
Interconnect parasitics
Operating conditions
: Uncertainty in environmental conditions during
the operation of a chip (power supply, temperature, etc.)
The distribution of gate delays (
pdf
or CDF) can be in any
form: normal, uniform, etc...
SSTA computes node and path delay distributions
and estimate
the
circuit delay
as the
joint distributions
The
distribution of circuit delays
can be represented by
continuous or
discrete functions
(either
pdf
or CDF)
Key difference between STA and SSTA
: Single values
versus distribution functions
Chapter 5: Timing Analysis and Optimization
5-58

Some Fundamentals
Chapter 5: Timing Analysis and Optimization
1
2
2
2
1
2
2
2
;
for
;
1
1
Shift:
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5-59

Chapter 5: Timing Analysis and Optimization
2
2
Joint
Joint
If
and
are independent the
,
,
,
;
,
,
:
,
,
n
XY
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12
1
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(
,
Uniform distrib
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ution
Gaussian (Normal)
2
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5-60