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If the source of the delay is a level-sensitive latch, use the -level_sensitiveoption. This allows PrimeTime to determine the correct single-cycle timing constraint for paths from this port. Use the -clock_falloption to denote a negative level-sensitive latch; otherwise, the -level_sensitiveoption implies a positive level-sensitive latch.To see input delays on ports, use the report_port -input_delaycommand.To remove input delay information from ports or pins in the current design set using the set_input_delaycommand, use the remove_input_delaycommand. The default is to remove all input delay information in the port_pin_listoption.Using Input Ports Simultaneously for Clock and DataPrimeTime allows an input port to behave simultaneously as a clock and data port. You can use the timing_simultaneous_clock_data_port_compatibilityvariable to enable or disable the simultaneous behavior of the input port as a clock and data port. When this variable is false, the default, simultaneous behavior is enabled and you can use the set_input_delaycommand to define the timing requirements for input ports relative to a clock. In this situation, the following applies:•If you specify the set_input_delaycommand relative to a clock defined at the same port and the port has data sinks, the command is ignored and an error message is issued. There is only one signal coming to port, and it cannot be at the same time data relative to a clock and the clock signal itself.•If you specify the set_input_delaycommand relative to a clock defined at a different port and the port has data sinks, the input delay is set and controls data edges launched from the port relative to the clock.•Regardless of the location of the data port, if the clock port does not fanout to data sinks, the input delay on the clock port is ignored and you receive an error message.When you set the timing_simultaneous_clock_data_port_compatibilityvariable to true, the simultaneous behavior is disabled and the set_input_delaycommand defines the arrival time relative to a clock. In this situation, when an input port has a clock defined on it, PrimeTime considers the port exclusively as a clock port and imposes restriction on the data edges that are launched. PrimeTime also prevents setting input delays relative to another clock.
Chapter 8: Timing Analysis ConditionsOutput Delays8-4PrimeTime Fundamentals User GuideF-2011.06PrimeTime Fundamentals User GuideVersion F-2011.06To control the clock source latency for any clocks defined on an input port, you must use the set_clock_latencycommand.Output DelaysTheset_output_delay command specifies output delays. An output delay represents an external timing path from an output port to a register. The maximum output delay value should be equal to the length of the longest path to the register data pin, plus the setup time of the register. The minimum output delay value should be equal to the length of the shortest path to the register data pin, minus the hold time.