When writing a data byte with fewer than 8 bits make sure the value is right

When writing a data byte with fewer than 8 bits make

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appropriate value into the bit count (BC) bits of I2CMDR. When writing a data byte with fewer than 8 bits, make sure the value is right-aligned in I2CDXR. After a data byte is written to I2CDXR, the I2C module copies the data byte to the transmit shift register (I2CXSR). The CPU cannot access I2CXSR directly. From I2CXSR, the I2C module shifts the data byte out on the SDA pin, one bit at a time. When in the transmit FIFO mode, the I2CDXR register acts as the transmit FIFO buffer. Figure 29. I2C Data Transmit Register (I2CDXR) 15 8 7 0 Reserved DATA R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 20. I2C Data Transmit Register (I2CDXR) Field Descriptions Bit Field Value Description 15-8 Reserved These reserved bit locations are always read as zeros. A value written to this field has no effect. 7-0 DATA Transmit data The I2C transmit FIFO register (I2CFFTX) is a 16-bit register that contains the I2C FIFO mode enable bit as well as the control and status bits for the transmit FIFO mode of operation on the I2C peripheral. The bit fields are shown in Figure 30 and described in Table 21 . Figure 30. I2C Transmit FIFO Register (I2CFFTX) 15 14 13 12 11 10 9 8 Reserved I2CFFEN TXFFRST TXFFST4 TXFFST3 TXFFST2 TXFFST1 TXFFST0 R-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0