For example a register loadstore will require 4

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For example, a register load/store will require 4 instruction bytes (1 for the opcode, 1 for the register destination/source, and 2 for a memory address) to be fetched from memory along with 4 data bytes. A memory-memory add instruction will require 7 instruction bytes (1 for the opcode and 2 for each of the 3 memory addresses) to be fetched from memory and will result in 12 data bytes being transferred (8 from memory to the processor and 4 from the processor back to memory). The following table displays a summary of this information for each of the architectural styles for the code: ISA Style Instruction for a = b + c Code bytes Data bytes Accumulator 3 3 + 3 + 3 4 + 4 + 4 Memory to Memory 1 7 Stack 4 3 + 3 + 1 + 3 4 + 4 + 0 + 4 Load-Store 4 4 + 4 + 3 + 4 4 + 4 + 0 + 4 For the following C code, write an equivalent assembly language program in each architectural style (assume all variables are initially in memory): a = b + c; b = a + c; d = a b; For each code sequence, calculate the instruction bytes fetched and the memory data bytes transferred (read or written). Which architecture is most efficient as measured by code size? Which architecture is most efficient as measured by total memory bandwidth required (code + data)? If the answers are not the same, why are they different?12

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