Professor n cheung uc berkeley lecture 19 ee143 f2010

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Professor N Cheung, U.C. Berkeley Lecture 19 EE143 F2010 Define active areas; etch Si trenches Fill trenches (deposit SiO 2 then CMP) Twin Well + STI CMOS Process Form wells (implantation + thermal anneal) Grow gate oxide Deposit poly-Si and pattern gate electrodes Implant source/drain and body-contact regions Activate dopants (thermal anneal) Deposit insulating layer (SiO 2 ); planarize (CMP) Open contact holes; deposit & pattern metal layer
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Professor N Cheung, U.C. Berkeley Lecture 19 EE143 F2010 9 3D view of a CMOS inverter after contact etch.
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Professor N Cheung, U.C. Berkeley Lecture 19 EE143 F2010 10 Well Engineering P-tub N-tub Twin Tub
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Professor N Cheung, U.C. Berkeley Lecture 19 EE143 F2010 11 Twin Well CMOS Process Flow
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