end initial begin reset end task reset routerresetn 1b0 routercbframen 16hffff

End initial begin reset end task reset routerresetn

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end initial begin reset(); end task reset(); router.reset_n <= 1’b0; router.cb.frame_n <= 16’hffff; router.cb.valid_n <= ~(’b0); ##2 router.cb.reset_n <= 1’b1; // reset_n can be both synchronous and asynchronous repeat(15) @(router.cb); endtask endprogram Sample Testbench square6 Develop test program code in initial block interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; ... clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; ... endclocking modport TB(clocking cb, output reset_n); endinterface Asynchronous signals are driven without reference to clocking block Advance clock cycles via clocking block Synchronous signals are driven via clocking block
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SystemVerilog Verification Environment SVTB 2-13 © 2006 13 2- Driving Synchronous Device Signals square6 Must be driven with <= (non-blocking assignment) square6 Can be specified with ##num of clocks delay Equivalent to: repeat(num) @(router.cb); router.din[3] <= #input_skew_value var_a; router.cb.din[3] = 1’b1; // error (must be non-blocking) var_a din[3] ##1 router.cb.din[3] <= var_a; clock Statement executes here Variable expression evaluates Apply drive here Next statement executes [## num ] interface. cb .signal <= < value > or < variable expression >;
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SystemVerilog Verification Environment SVTB 2-14 © 2006 14 2- Sampling Synchronous Device Signals square6 No delay attribute (## num ) square6 Variable is assigned the sampled value square6 Sampling of output signal is not allowed Examples: data[i] = router.cb.dout[7]; all_data = router.cb.dout; @(posedge router.cb.frameo_n[7]); $display(“router.cb.din = %b\n”, router.din); //error if(router.cb.din[3] == 1’b0) //error variable = interface.cb.signal;
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SystemVerilog Verification Environment SVTB 2-15 © 2006 15 2- Advancing Simulation Time square6 Asynchronous (Verilog coding style): #delay; @(negedge interface.signal); square6 Synchronous (advancing clock cycles): circle6 Verilog coding style: @(posedge interface.clock_signal); repeat (10) @(posedge interface.clock_signal); circle6 SystemVerilog coding style (clocking block): @(interface.clocking_block); repeat (10) @(interface.clocking_block); rhombus6 Each clocking block specifies a clock signal and edge: interface router_io(input logic clock); clocking cb @(posedge clock); ... endclocking endinterface In order for the syntax @(posedge interface.clock_signal); to work. The clock_signal must be passed in as an additional asynchronous signal argument to the modport for the test program connection: interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ; clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; input dout; input busy_n; input valido_n; input frameo_n; endclocking modport TB(clocking cb, output reset_n, input clock ); endinterface
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SystemVerilog Verification Environment SVTB 2-16 © 2006 16 2- module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; wire reset_n ; wire clock ; wire [15:0] frame_n ; wire [15:0] valid_n ; wire [15:0] din ; wire [15:0] dout ; wire [15:0]
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