For example you might start by using inverters just

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For example, you might start by using inverters just to connect inputs directly to the outputs. You expand these stubs before moving down to the next level of modules. module MyChip_ASIC() // behavioral "always", etc. ... SecondLevelStub1 port mapping SecondLevelStub2 port mapping ... endmodule module SecondLevelStub1() ... assign Output1 = ~Input1; endmodule module SecondLevelStub2() ... assign Output2 = ~Input2; endmodule Eventually the Verilog modules will correspond to the various component pieces of the ASIC.
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Verilog Modeling Before we could start synthesis of the Viterbi decoder we had to alter the model for the D flip-flop. This was because the original flip-flop model contained syntax (multiple wait statements in an always statement) that was acceptable to the simulation tool but not by the synthesis tool. However, finding ourselves with non-synthesizable code arises frequently in logic synthesis. The original OVI LRM included a synthesis policy , a set of guidelines that outline which parts of the Verilog language a synthesis tool should support and which parts are optional. There is no current standard on which parts of an HDL (either Verilog or VHDL) a synthesis tool should support.
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It is essential that the structural model created by a synthesis tool is functionally identical , or functionally equivalent , to your behavioral model. Hopefully, we know this is true if the synthesis tool is working properly. In this case the logic is “correct by construction.” If you use different HDL code for simulation and for synthesis, you have a problem. The process offormal verification can prove that two logic descriptions (perhaps structural and behavioral HDL descriptions) are identical in their behavior.
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Delays in Verilog Synthesis tools ignore delay values. They must—how can a synthesis tool guarantee that logic will have a certain delay? For example, a synthesizer cannot generate hardware to implement the following Verilog code: module Step_Time(clk, phase); input clk; output [2:0] phase; reg [2:0] phase; always @( posedge clk) begin phase <= 4'b0000; phase <= #1 4'b0001; phase <= #2 4'b0010; phase <= #3 4'b0011; phase <= #4 4'b0100; end endmodule
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We can avoid this type of timing problem by dividing a clock as follows: module Step_Count (clk_5x, phase); input clk_5x; output [2:0] phase; reg [2:0] phase; always @( posedge clk_5x) case (phase) 0:phase = #1 1; 1:phase = #1 2; 2:phase = #1 3; 3:phase = #1 4; default : phase = #1 0; endcase endmodule
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Blocking and Nonblocking Assignments There are some synthesis limitations that arise from the different types of Verilog assignment statements. Consider the following shift-register model: module race(clk, q0); input clk, q0; reg q1, q2; always @( posedge clk) q1 = #1 q0; always @( posedge clk) q2 = #1 q1; Endmodule This example has a race condition (or a race ) that occurs as follows.
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  • Fall '15
  • prasad
  • Logic, Electronic design automation, Logic Synthesis, ASIC

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