The remaining question we are going to do a hands on

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The remaining question, we are going to do a hands-on activity slash learning experience for troubleshooting a circuit. At the end of this lab, you will able to gain further knowledge of multisim tool and how they operator.
TWoodroffe 3 1. Circuit F11-06 A. Objective : Refer to Example 11-1 in your text. Observe the operation of a 5-bit Register. In this lab the MultiSim Logic Analyzer is already connected for you. There is also a Word Generator connected as the input. The word generator sends digital words or patterns of bits into circuits to provide stimulus to digital circuits. Figure 1 : The simulation of the circuit of the 5-bit Register. B. Observation: When I activated the simulation, I observed how the 1 st bit was plugged into the register for the first clock pulse. After it had entered, I observed the word generator where the reading showed the 1s and 0s were shifting one after another. This circuit demonstrates the transferring of the bits in a serial-in/serial out shift register.
TWoodroffe 4 C. Conclusion: When I read the passage of chapter 11, I have gained an understanding of how this 5-bit Register works. The first data plugged into the register, produced a shift from left to right as the remaining bits entered and shifted. This also includes verifying the example 11-1 that matched the actual value of the simulation. Related problem: Show the states of the register if the data input is inverted. The register is initially cleared. Figure 2: The result for the related problem. 2. Circuit F11-12 A. Objective: Observe the operation of a 4-bit Parallel In/Serial Out Register. In this lab the MultiSim Logic Analyzer is already connected for you. There is also a Word Generator
TWoodroffe 5 connected as the input. The word generator sends digital words or patterns of bits into circuits to provide stimulus to digital circuits. Include a drawing or screen capture that reflects the observed timing diagram in your lab summary report. Figure 1: Circuit F11-12.
TWoodroffe 6 B. Observation: The simulation of 4-bit Parallel In/Serial Out Register was successful. I noticed that the section on register appears that the data input has more than one lines which include shift/ ´ load as efficient connections. C. Conclusion: This led me to believe that this allows the four bits of data transfer to load in a parallel with the register. The result suggested that the Shift/ ´ Load is low and G1 to G4 enabled. This allows the individuals data bit to be linked to D input of its sign flip-flop.

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