Bits pilani deemed to be university under section 3

This preview shows page 12 - 22 out of 59 pages.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Memory Location, Addresses, and Operation Address ordering of bytes Word alignment Words are said to be aligned in memory if they begin at a byte address. that is a multiple of the number of bytes in a word. 16-bit word: word addresses: 0, 2, 4,…. 32-bit word: word addresses: 0, 4, 8,…. 64-bit word: word addresses: 0, 8,16,….
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Memory Operation Load (or Read or Fetch) Copy the content. The memory content doesn’t change. Address – Load Registers can be used Store (or Write) Overwrite the content in memory Address and Data – Store Registers can be used
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 “Must-Perform” Operations Data transfers between the memory and the processor registers Arithmetic and logic operations on data Program sequencing and control I/O transfers
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Register Transfer Notation Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,…) Contents of a location are denoted by placing square brackets around the name of the location (R1←[LOC], R3 ←[R1]+[R2]) Register Transfer Notation (RTN)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Assembly Language Notation Represent machine instructions and programs. Move LOC, R1 = R1←[LOC] Add R1, R2, R3 = R3 ←[R1]+[R2] or Add R1, R2, R3 = R1 ←[R2]+[R3]
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 CPU Organization Single Accumulator Result usually goes to the Accumulator Accumulator has to be saved to memory quite often General Register Registers hold operands thus reduce memory traffic Register book keeping Stack Operands and result are always in the stack
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Instruction Formats Three-Address Instructions ADD R1, R2, R3 R1 ← R2 + R3 or R3 ← R1 + R2 Two-Address Instructions ADD R1, R2 R1 ← R1 + R2 One-Address Instructions ADD M AC ← AC + M[AR] Zero-Address Instructions ADD TOS ← TOS + (TOS – 1) RISC Instructions Lots of registers. Memory is restricted to Load & Store Instruction Opcode Operand(s) or Address(es)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Instruction Formats Example: Evaluate (A+B) (C+D) Three-Address 1. ADD R1, A, B ; R1 ← M[A] + M[B] 2. ADD R2, C, D ; R2 ← M[C] + M[D] 3. MUL X, R1, R2 ; M[X] ← R1 R2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Instruction Formats Example: Evaluate (A+B) (C+D) Two-Address 1. MOV R1, A ; R1 ← M[A] 2. ADD R1, B ; R1 ← R1 + M[B] 3. MOV R2, C ; R2 ← M[C] 4. ADD R2, D ; R2 ← R2 + M[D] 5. MUL R1, R2 ; R1 ← R1 R2 6. MOV X, R1 ; M[X] ← R1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Instruction Formats Example: Evaluate (A+B) (C+D) One-Address 1.

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture