X Y F 52V 13V Q1 Q2 Q3 Q3 Figure 717 Emitter Coupled OR gate 6 MOS Logic MOS

X y f 52v 13v q1 q2 q3 q3 figure 717 emitter coupled

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XYF-5.2V-1.3VQ1Q2Q3Q3Figure 7.17 Emitter Coupled OR gate 6.MOS Logic MOS (metal oxide semiconductor) logic gates can be evolved from RTL logics by replacing BJTs with their equivalent MOSFET and the output resistor with MOSFET based active load. For example, the CMOS counter of RTL Inverter, NOR and NAND gates, are developed using n-channel MOS transistor as in the figure 7.18
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Applied Electronic II ASTU EENG 3203 10 Electrical Engineering Figure 7.18 MOS logic gates 7.CMOS Logic Gates CMOS circuits are built using both the NMOS (n-channel MODFETs) and PMOS (p-channel MOSFETs) transistors. Because of the inherent properties of the NMOS and PMOS transistors, CMOS circuits are always built with two halves. One half will use one transistor type while the other half will use the other type, and when combined together to form the complete circuit, they will work in complement of each other. The logic symbols and operations for the NMOS and PMOS transistors are shown in Figure 6.19 and Figure 6.20, respectively. The operation of the NMOS transistor is shown in Figure 6.19(b). The biggest attraction towards CMOS technology is due to the added opportunity of designing the logic circuit so that there could not be unwanted power dissipation whenever there is no input. Consequently, for proper operation of NMOS transistor, the input is connected to the gate terminal, one terminal, say source, is grounded and the output is taken at the drain. For this configuration, when the gate is 1, the NMOS transistor is turned on or enabled, thereby pulling the output to the ground level. However, when the gate is a 0, the transistor is turned off, and the connection between the source and the drain is disconnected. Thus, This NMOS configuration is inverter of 1 and used to output the 0 half of the truth table. Gate (input) Status of Transistor Output 0 Open Circuited High impedance 1 Short Circuited 0
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Applied Electronic II ASTU EENG 3203 11 Electrical Engineering Figure 7.19 NMOS transistor: (a) logic symbol; (b) truth table. The PMOS transistor works exactly the opposite of the NMOS transistor. For the PMOS transistor, the source is the terminal with the higher voltage with respect to the drain. We can intuitively think of the source as the terminal that is supplying the 1 value, while the drain consumes the 1 value. The operation of the PMOS transistor is shown in Figure 6.20(b). When the gate is a 0, the PMOS transistor is turned on or enabled, and the source input that is supplying the 1 can pass through to the drain output through the connecting p-channel. On the other hand, when the gate is a 1, the transistor is turned off, and the connection between the source and the drain is disconnected. In this case, the drain will always have a high-impedance value. Thus, this PMOS configuration is inverter of 0 and used to output the 1 half of the truth table.
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  • Fall '19
  • Logic gate

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