A high precision1024 point fft processor for 2d

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“A high precision1024-point FFT processor for 2D convolution,” M. Wosnitza, M. Cavadini, M. Thaler, and G. Troster, in Proc. IEEE Int. Solid-State Circuits Conf., 1998, vol. 41, pp. 118–119, 424. “A radix 4 delay commutator for fast Fourier transform processor implementation” Swartzlander, E.E.; Young, W.K.W.; Joseph, S.J.; Solid-State Circuits, IEEE Journal of ,Volume: 19 , Issue: 5 , Oct 1984 Pages:702 - 709 “A VLSI array processor for 16-point FFT” Lee, Moon-Key; Shin, Kyung-Wook; Lee, Jang-Kyu; Solid-StateCircuits, IEEE Journal of ,Volume: 26 , Issue: 9 , Sept. 1991 Pages:1286 – 1292 3. Digital PLL Phase-lock loops (PLLs) are used to recover timing information from a signal—they are ubiquitous in communications, and are also used for timing recovery on boards and chips. Analog PLLs are very hard to design because they use feedback, and are very sensitive to noise and operating parameters. The goal of this project is to design a pure digital PLL and compare its performance (measured in lock time and phase noise) and costs (in terms of area, power, delay) to a traditional analog PLL. Some of the papers that can be referred are “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors” Jim Dunning, , Gerald Garcia , Jim Lundberg, and Ed Nuckolls , IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30 , NO. 4 , APRIL 1995 R. E. Best, Phase-Locked Loops, Theory, Design and Applications. New York: McGraw-Hill, 1993, 2nd ed. “A Digitally Controlled PLL for SoC Applications” Thomas Olsson , and Peter Nilsson IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 751 “A fully integrated standard-cell digital PLL,” T. Olsson and P. Nilsson, IEEElectron. Lett. , vol. 37, pp. 211–212, Feb. 2001. 4. High-Speed N-bit Kogge-Stone Adder (N >= 32) The KS-adder utilizes a parallel-prefix topology to reduce the critical path in the adder. The critical path, which is the carry generation path, has a logarithmic dependence of the bit-width. This should be compared to the linear dependence in the ripple carry adder. There are many ways to implement the carry generation tree for parallel prefix adders, but KS implementation is the most straightforward, and also it has one of the shortest critical paths of all tree adders. The drawback with the KS implementation is the large area consumed and the somewhat complex routing of interconnects. If you have a 16 bit adder, you will have 32 input pads and 16 output pads. This accounts to 48 pads which is too much. Because of the limited amount of pads a bit serial-to-parallel input/output interface (SPI) must be used to feed input vectors to the adder and get back the output. The inputs are feed to the circuit in a bit-serial data stream and are converted into N-bit vectors by the serial to parallel converters. Outputs of the sum vector are gotten through a parallel-to-serial interface. In addition to speed, use low power techniques to minimize power as well.
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J.M. Rabaey, A. Chandrakasan, and B. Nikolic.,
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